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1 | | -SPI (Serial Peripheral Interface) busses |
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2 | | - |
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3 | | -SPI busses can be described with a node for the SPI controller device |
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4 | | -and a set of child nodes for each SPI slave on the bus. The system's SPI |
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5 | | -controller may be described for use in SPI master mode or in SPI slave mode, |
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6 | | -but not for both at the same time. |
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7 | | - |
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8 | | -The SPI controller node requires the following properties: |
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9 | | -- compatible - Name of SPI bus controller following generic names |
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10 | | - recommended practice. |
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11 | | - |
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12 | | -In master mode, the SPI controller node requires the following additional |
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13 | | -properties: |
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14 | | -- #address-cells - number of cells required to define a chip select |
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15 | | - address on the SPI bus. |
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16 | | -- #size-cells - should be zero. |
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17 | | - |
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18 | | -In slave mode, the SPI controller node requires one additional property: |
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19 | | -- spi-slave - Empty property. |
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20 | | - |
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21 | | -No other properties are required in the SPI bus node. It is assumed |
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22 | | -that a driver for an SPI bus device will understand that it is an SPI bus. |
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23 | | -However, the binding does not attempt to define the specific method for |
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24 | | -assigning chip select numbers. Since SPI chip select configuration is |
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25 | | -flexible and non-standardized, it is left out of this binding with the |
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26 | | -assumption that board specific platform code will be used to manage |
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27 | | -chip selects. Individual drivers can define additional properties to |
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28 | | -support describing the chip select layout. |
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29 | | - |
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30 | | -Optional properties (master mode only): |
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31 | | -- cs-gpios - gpios chip select. |
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32 | | -- num-cs - total number of chipselects. |
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33 | | - |
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34 | | -If cs-gpios is used the number of chip selects will be increased automatically |
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35 | | -with max(cs-gpios > hw cs). |
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36 | | - |
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37 | | -So if for example the controller has 2 CS lines, and the cs-gpios |
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38 | | -property looks like this: |
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39 | | - |
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40 | | -cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; |
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41 | | - |
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42 | | -Then it should be configured so that num_chipselect = 4 with the |
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43 | | -following mapping: |
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44 | | - |
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45 | | -cs0 : &gpio1 0 0 |
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46 | | -cs1 : native |
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47 | | -cs2 : &gpio1 1 0 |
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48 | | -cs3 : &gpio1 2 0 |
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49 | | - |
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50 | | - |
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51 | | -SPI slave nodes must be children of the SPI controller node. |
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52 | | - |
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53 | | -In master mode, one or more slave nodes (up to the number of chip selects) can |
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54 | | -be present. Required properties are: |
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55 | | -- compatible - Name of SPI device following generic names recommended |
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56 | | - practice. |
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57 | | -- reg - Chip select address of device. |
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58 | | -- spi-max-frequency - Maximum SPI clocking speed of device in Hz. |
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59 | | - |
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60 | | -In slave mode, the (single) slave node is optional. |
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61 | | -If present, it must be called "slave". Required properties are: |
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62 | | -- compatible - Name of SPI device following generic names recommended |
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63 | | - practice. |
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64 | | - |
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65 | | -All slave nodes can contain the following optional properties: |
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66 | | -- spi-cpol - Empty property indicating device requires inverse clock |
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67 | | - polarity (CPOL) mode. |
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68 | | -- spi-cpha - Empty property indicating device requires shifted clock |
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69 | | - phase (CPHA) mode. |
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70 | | -- spi-cs-high - Empty property indicating device requires chip select |
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71 | | - active high. |
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72 | | -- spi-3wire - Empty property indicating device requires 3-wire mode. |
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73 | | -- spi-lsb-first - Empty property indicating device requires LSB first mode. |
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74 | | -- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. |
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75 | | - Defaults to 1 if not present. |
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76 | | -- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO. |
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77 | | - Defaults to 1 if not present. |
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78 | | -- spi-rx-delay-us - Microsecond delay after a read transfer. |
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79 | | -- spi-tx-delay-us - Microsecond delay after a write transfer. |
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80 | | - |
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81 | | -Some SPI controllers and devices support Dual and Quad SPI transfer mode. |
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82 | | -It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4 |
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83 | | -wires (QUAD). |
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84 | | -Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is |
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85 | | -only 1 (SINGLE), 2 (DUAL) and 4 (QUAD). |
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86 | | -Dual/Quad mode is not allowed when 3-wire mode is used. |
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87 | | - |
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88 | | -If a gpio chipselect is used for the SPI slave the gpio number will be passed |
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89 | | -via the SPI master node cs-gpios property. |
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90 | | - |
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91 | | -SPI example for an MPC5200 SPI bus: |
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92 | | - spi@f00 { |
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93 | | - #address-cells = <1>; |
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94 | | - #size-cells = <0>; |
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95 | | - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
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96 | | - reg = <0xf00 0x20>; |
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97 | | - interrupts = <2 13 0 2 14 0>; |
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98 | | - interrupt-parent = <&mpc5200_pic>; |
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99 | | - |
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100 | | - ethernet-switch@0 { |
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101 | | - compatible = "micrel,ks8995m"; |
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102 | | - spi-max-frequency = <1000000>; |
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103 | | - reg = <0>; |
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104 | | - }; |
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105 | | - |
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106 | | - codec@1 { |
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107 | | - compatible = "ti,tlv320aic26"; |
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108 | | - spi-max-frequency = <100000>; |
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109 | | - reg = <1>; |
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110 | | - }; |
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111 | | - }; |
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| 1 | +This file has moved to spi-controller.yaml. |
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