移去rt

hc

2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/serial/mtk-uart.txt
..
..
@@ -1,4 +1,4 @@
1
-* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
1
+* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
2
2
 
3
3
 Required properties:
4
4
 - compatible should contain:
..
..
@@ -9,18 +9,28 @@
9
9
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10
10
   * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11
11
   * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12
+  * "mediatek,mt6779-uart" for MT6779 compatible UARTS
12
13
   * "mediatek,mt6795-uart" for MT6795 compatible UARTS
13
14
   * "mediatek,mt6797-uart" for MT6797 compatible UARTS
14
15
   * "mediatek,mt7622-uart" for MT7622 compatible UARTS
15
16
   * "mediatek,mt7623-uart" for MT7623 compatible UARTS
17
+  * "mediatek,mt7629-uart" for MT7629 compatible UARTS
16
18
   * "mediatek,mt8127-uart" for MT8127 compatible UARTS
17
19
   * "mediatek,mt8135-uart" for MT8135 compatible UARTS
18
20
   * "mediatek,mt8173-uart" for MT8173 compatible UARTS
21
+  * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
22
+  * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
23
+  * "mediatek,mt8516-uart" for MT8516 compatible UARTS
19
24
   * "mediatek,mt6577-uart" for MT6577 and all of the above
20
25
 
21
26
 - reg: The base address of the UART register bank.
22
27
 
23
-- interrupts: A single interrupt specifier.
28
+- interrupts:
29
+  index 0: an interrupt specifier for the UART controller itself
30
+  index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to
31
+           support Rx in-band wake up. If one would like to use this feature,
32
+           one must create an addtional pinctrl to reconfigure Rx pin to normal
33
+           GPIO before suspend.
24
34
 
25
35
 - clocks : Must contain an entry for each entry in clock-names.
26
36
   See ../clocks/clock-bindings.txt for details.
..
..
@@ -36,7 +46,11 @@
36
46
 	uart0: serial@11006000 {
37
47
 		compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
38
48
 		reg = <0x11006000 0x400>;
39
-		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
49
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
50
+			     <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
40
51
 		clocks = <&uart_clk>, <&bus_clk>;
41
52
 		clock-names = "baud", "bus";
53
+		pinctrl-names = "default", "sleep";
54
+		pinctrl-0 = <&uart_pin>;
55
+		pinctrl-1 = <&uart_pin_sleep>;
42
56
 	};