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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/reset/uniphier-reset.txt
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@@ -1,149 +1,34 @@
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-UniPhier reset controller
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+UniPhier glue reset controller
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-System reset
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-------------
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+Peripheral core reset in glue layer
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+-----------------------------------
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-Required properties:
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-- compatible: should be one of the following:
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-    "socionext,uniphier-ld4-reset"  - for LD4 SoC
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-    "socionext,uniphier-pro4-reset" - for Pro4 SoC
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-    "socionext,uniphier-sld8-reset" - for sLD8 SoC
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-    "socionext,uniphier-pro5-reset" - for Pro5 SoC
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-    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
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-    "socionext,uniphier-ld11-reset" - for LD11 SoC
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-    "socionext,uniphier-ld20-reset" - for LD20 SoC
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-    "socionext,uniphier-pxs3-reset" - for PXs3 SoC
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-- #reset-cells: should be 1.
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-
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-Example:
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-
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-	sysctrl@61840000 {
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-		compatible = "socionext,uniphier-ld11-sysctrl",
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-			     "simple-mfd", "syscon";
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-		reg = <0x61840000 0x4000>;
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-
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-		reset {
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-			compatible = "socionext,uniphier-ld11-reset";
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-			#reset-cells = <1>;
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-		};
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-
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-		other nodes ...
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-	};
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-
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-
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-Media I/O (MIO) reset, SD reset
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--------------------------------
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-
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-Required properties:
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-- compatible: should be one of the following:
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-    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC
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-    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
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-    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
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-    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC
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-    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC
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-    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
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-    "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)
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-    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC
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-    "socionext,uniphier-pxs3-sd-reset"  - for PXs3 SoC
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-- #reset-cells: should be 1.
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-
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-Example:
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-
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-	mioctrl@59810000 {
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-		compatible = "socionext,uniphier-ld11-mioctrl",
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-			     "simple-mfd", "syscon";
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-		reg = <0x59810000 0x800>;
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-
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-		reset {
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-			compatible = "socionext,uniphier-ld11-mio-reset";
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-			#reset-cells = <1>;
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-		};
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-
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-		other nodes ...
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-	};
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-
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-
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-Peripheral reset
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-----------------
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-
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-Required properties:
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-- compatible: should be one of the following:
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-    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC
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-    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC
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-    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC
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-    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC
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-    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
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-    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
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-    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
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-    "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
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-- #reset-cells: should be 1.
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-
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-Example:
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-
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-	perictrl@59820000 {
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-		compatible = "socionext,uniphier-ld11-perictrl",
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-			     "simple-mfd", "syscon";
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-		reg = <0x59820000 0x200>;
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-
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-		reset {
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-			compatible = "socionext,uniphier-ld11-peri-reset";
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-			#reset-cells = <1>;
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-		};
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-
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-		other nodes ...
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-	};
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-
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-
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-Analog signal amplifier reset
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------------------------------
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-
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-Required properties:
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-- compatible: should be one of the following:
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-    "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
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-    "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
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-- #reset-cells: should be 1.
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-
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-Example:
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-
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-	adamv@57920000 {
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-		compatible = "socionext,uniphier-ld11-adamv",
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-			     "simple-mfd", "syscon";
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-		reg = <0x57920000 0x1000>;
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-
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-		adamv_rst: reset {
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-			compatible = "socionext,uniphier-ld11-adamv-reset";
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-			#reset-cells = <1>;
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-		};
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-
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-		other nodes ...
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-	};
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-
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-
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-USB3 core reset
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----------------
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-
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-USB3 core reset belongs to USB3 glue layer. Before using the core reset,
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-it is necessary to control the clocks and resets to enable this layer.
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-These clocks and resets should be described in each property.
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+Some peripheral core reset belongs to its own glue layer. Before using
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+this core reset, it is necessary to control the clocks and resets to enable
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+this layer. These clocks and resets should be described in each property.
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 Required properties:
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 - compatible: Should be
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-    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
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-    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
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-    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
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-    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
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+    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
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+    "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
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+    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
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+    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
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+    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
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+    "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
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+    "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
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+    "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
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 - #reset-cells: Should be 1.
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 - reg: Specifies offset and length of the register set for the device.
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-- clocks: A list of phandles to the clock gate for USB3 glue layer.
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+- clocks: A list of phandles to the clock gate for the glue layer.
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 	According to the clock-names, appropriate clocks are required.
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 - clock-names: Should contain
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-    "gio", "link" - for Pro4 SoC
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+    "gio", "link" - for Pro4 and Pro5 SoCs
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     "link"        - for others
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-- resets: A list of phandles to the reset control for USB3 glue layer.
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+- resets: A list of phandles to the reset control for the glue layer.
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 	According to the reset-names, appropriate resets are required.
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 - reset-names: Should contain
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-    "gio", "link" - for Pro4 SoC
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+    "gio", "link" - for Pro4 and Pro5 SoCs
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     "link"        - for others
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 Example: