.. | .. |
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4 | 4 | 2 USB PHY contains. |
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5 | 5 | |
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6 | 6 | Required properties: |
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7 | | -- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. |
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| 7 | +- compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC. |
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| 8 | + "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. |
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| 9 | + "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC. |
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8 | 10 | "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. |
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| 11 | + "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC. |
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9 | 12 | "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. |
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10 | 13 | "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. |
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11 | 14 | "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. |
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.. | .. |
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29 | 32 | - #phy-cells: see phy-bindings.txt in the same directory, must be <1>. |
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30 | 33 | |
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31 | 34 | The phandle's argument in the PHY specifier is the USB controller selector for |
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32 | | -the USB channel; see the selector meanings below: |
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| 35 | +the USB channel other than r8a77470 SoC; see the selector meanings below: |
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33 | 36 | |
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34 | 37 | +-----------+---------------+---------------+ |
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35 | 38 | |\ Selector | | | |
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.. | .. |
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40 | 43 | | 2 | PCI EHCI/OHCI | xHCI | |
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41 | 44 | +-----------+---------------+---------------+ |
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42 | 45 | |
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| 46 | +For r8a77470 SoC;see the selector meaning below: |
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| 47 | + |
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| 48 | ++-----------+---------------+---------------+ |
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| 49 | +|\ Selector | | | |
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| 50 | ++ --------- + 0 | 1 | |
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| 51 | +| Channel \| | | |
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| 52 | ++-----------+---------------+---------------+ |
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| 53 | +| 0 | EHCI/OHCI | HS-USB | |
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| 54 | ++-----------+---------------+---------------+ |
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| 55 | + |
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43 | 56 | Example (Lager board): |
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44 | 57 | |
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45 | 58 | usb-phy@e6590100 { |
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.. | .. |
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47 | 60 | reg = <0 0xe6590100 0 0x100>; |
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48 | 61 | #address-cells = <1>; |
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49 | 62 | #size-cells = <0>; |
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50 | | - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; |
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| 63 | + clocks = <&cpg CPG_MOD 704>; |
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51 | 64 | clock-names = "usbhs"; |
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| 65 | + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; |
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| 66 | + resets = <&cpg 704>; |
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52 | 67 | |
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53 | | - usb-channel@0 { |
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| 68 | + usb0: usb-channel@0 { |
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54 | 69 | reg = <0>; |
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55 | 70 | #phy-cells = <1>; |
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56 | 71 | }; |
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57 | | - usb-channel@2 { |
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| 72 | + usb2: usb-channel@2 { |
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58 | 73 | reg = <2>; |
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59 | 74 | #phy-cells = <1>; |
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60 | 75 | }; |
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61 | 76 | }; |
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| 77 | + |
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| 78 | +Example (iWave RZ/G1C sbc): |
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| 79 | + |
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| 80 | + usbphy0: usb-phy0@e6590100 { |
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| 81 | + compatible = "renesas,usb-phy-r8a77470", |
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| 82 | + "renesas,rcar-gen2-usb-phy"; |
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| 83 | + reg = <0 0xe6590100 0 0x100>; |
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| 84 | + #address-cells = <1>; |
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| 85 | + #size-cells = <0>; |
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| 86 | + clocks = <&cpg CPG_MOD 704>; |
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| 87 | + clock-names = "usbhs"; |
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| 88 | + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; |
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| 89 | + resets = <&cpg 704>; |
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| 90 | + |
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| 91 | + usb0: usb-channel@0 { |
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| 92 | + reg = <0>; |
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| 93 | + #phy-cells = <1>; |
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| 94 | + }; |
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| 95 | + }; |
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| 96 | + |
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| 97 | + usbphy1: usb-phy@e6598100 { |
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| 98 | + compatible = "renesas,usb-phy-r8a77470", |
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| 99 | + "renesas,rcar-gen2-usb-phy"; |
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| 100 | + reg = <0 0xe6598100 0 0x100>; |
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| 101 | + #address-cells = <1>; |
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| 102 | + #size-cells = <0>; |
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| 103 | + clocks = <&cpg CPG_MOD 706>; |
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| 104 | + clock-names = "usbhs"; |
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| 105 | + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; |
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| 106 | + resets = <&cpg 706>; |
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| 107 | + |
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| 108 | + usb1: usb-channel@0 { |
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| 109 | + reg = <0>; |
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| 110 | + #phy-cells = <1>; |
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| 111 | + }; |
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| 112 | + }; |
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