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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
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@@ -13,10 +13,16 @@
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 		  "mediatek,mt8173-u3phy";
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 		  make use of "mediatek,generic-tphy-v1" on mt2701 instead and
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 		  "mediatek,generic-tphy-v2" on mt2712 instead.
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- - clocks	: (deprecated, use port's clocks instead) a list of phandle +
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-		  clock-specifier pairs, one for each entry in clock-names
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- - clock-names	: (deprecated, use port's one instead) must contain
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-		  "u3phya_ref": for reference clock of usb3.0 analog phy.
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+
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+- #address-cells:	the number of cells used to represent physical
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+		base addresses.
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+- #size-cells:	the number of cells used to represent the size of an address.
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+- ranges:	the address mapping relationship to the parent, defined with
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+		- empty value: if optional 'reg' is used.
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+		- non-empty value: if optional 'reg' is not used. should set
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+			the child's base address to 0, the physical address
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+			within parent's address space, and the length of
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+			the address map.
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 Required nodes	: a sub-node is required for each port the controller
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 		  provides. Address range information including the usual
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@@ -34,12 +40,6 @@
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 Required properties (port (child) node):
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 - reg		: address and length of the register set for the port.
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-- clocks	: a list of phandle + clock-specifier pairs, one for each
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-		  entry in clock-names
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-- clock-names	: must contain
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-		  "ref": 48M reference clock for HighSpeed analog phy; and 26M
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-			reference clock for SuperSpeed analog phy, sometimes is
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-			24M, 25M or 27M, depended on platform.
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 - #phy-cells	: should be 1 (See second example)
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 		  cell after port phandle is phy type from:
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 			- PHY_TYPE_USB2
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@@ -48,10 +48,22 @@
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 			- PHY_TYPE_SATA
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 Optional properties (PHY_TYPE_USB2 port (child) node):
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+- clocks	: a list of phandle + clock-specifier pairs, one for each
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+		  entry in clock-names
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+- clock-names	: may contain
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+		  "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
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+			reference clock for SuperSpeed (digital) phy, sometimes is
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+			24M, 25M or 27M, depended on platform.
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+		  "da_ref": the reference clock of analog phy, used if the clocks
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+			of analog and digital phys are separated, otherwise uses
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+			"ref" clock only if needed.
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+
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 - mediatek,eye-src	: u32, the value of slew rate calibrate
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 - mediatek,eye-vrt	: u32, the selection of VRT reference voltage
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 - mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage
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 - mediatek,bc12	: bool, enable BC12 of u2phy if support it
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+- mediatek,discth	: u32, the selection of disconnect threshold
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+- mediatek,intr	: u32, the selection of internal R (resistance)
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 Example:
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