.. | .. |
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11 | 11 | - reg-names: |
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12 | 12 | - "ctrl" for the control register region |
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13 | 13 | - "config" for the config space region |
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14 | | -- interrupts: Interrupt specifier for the PCIe controler |
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| 14 | +- interrupts: Interrupt specifier for the PCIe controller |
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15 | 15 | - clocks: reference to the PCIe controller clocks |
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16 | 16 | - clock-names: mandatory if there is a second clock, in this case the |
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17 | 17 | name must be "core" for the first clock and "reg" for the second |
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18 | 18 | one |
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19 | 19 | |
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| 20 | +Optional properties: |
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| 21 | +- phys: phandle(s) to PHY node(s) following the generic PHY bindings. |
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| 22 | + Either 1, 2 or 4 PHYs might be needed depending on the number of |
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| 23 | + PCIe lanes. |
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| 24 | +- phy-names: names of the PHYs corresponding to the number of lanes. |
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| 25 | + Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for |
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| 26 | + 2 PHYs. |
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| 27 | + |
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20 | 28 | Example: |
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21 | 29 | |
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22 | 30 | pcie@f2600000 { |
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