.. | .. |
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41 | 41 | 0x0 0 0 3 &mbigen_pcie 3 12 |
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42 | 42 | 0x0 0 0 4 &mbigen_pcie 4 13>; |
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43 | 43 | }; |
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44 | | - |
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45 | | -HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. |
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46 | | - |
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47 | | -Some BIOSes place the host controller in a mode where it is ECAM |
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48 | | -compliant for all devices other than the root complex. In such cases, |
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49 | | -the host controller should be described as below. |
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50 | | - |
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51 | | -The properties and their meanings are identical to those described in |
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52 | | -host-generic-pci.txt except as listed below. |
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53 | | - |
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54 | | -Properties of the host controller node that differ from |
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55 | | -host-generic-pci.txt: |
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56 | | - |
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57 | | -- compatible : Must be "hisilicon,hip06-pcie-ecam", or |
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58 | | - "hisilicon,hip07-pcie-ecam" |
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59 | | - |
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60 | | -- reg : Two entries: First the ECAM configuration space for any |
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61 | | - other bus underneath the root bus. Second, the base |
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62 | | - and size of the HiSilicon host bridge registers include |
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63 | | - the RC's own config space. |
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64 | | - |
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65 | | -Example: |
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66 | | - pcie0: pcie@a0090000 { |
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67 | | - compatible = "hisilicon,hip06-pcie-ecam"; |
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68 | | - reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ |
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69 | | - <0 0xa0090000 0 0x10000>; /* host bridge registers */ |
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70 | | - bus-range = <0 31>; |
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71 | | - msi-map = <0x0000 &its_dsa 0x0000 0x2000>; |
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72 | | - msi-map-mask = <0xffff>; |
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73 | | - #address-cells = <3>; |
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74 | | - #size-cells = <2>; |
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75 | | - device_type = "pci"; |
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76 | | - dma-coherent; |
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77 | | - ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000 |
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78 | | - 0x01000000 0 0 0 0xb7ff0000 0 0x10000>; |
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79 | | - #interrupt-cells = <1>; |
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80 | | - interrupt-map-mask = <0xf800 0 0 7>; |
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81 | | - interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 |
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82 | | - 0x0 0 0 2 &mbigen_pcie0 650 4 |
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83 | | - 0x0 0 0 3 &mbigen_pcie0 650 4 |
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84 | | - 0x0 0 0 4 &mbigen_pcie0 650 4>; |
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85 | | - }; |
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