移去rt

hc

2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
..
..
@@ -9,6 +9,7 @@
9
9
 	- "fsl,imx6sx-pcie",
10
10
 	- "fsl,imx6qp-pcie"
11
11
 	- "fsl,imx7d-pcie"
12
+	- "fsl,imx8mq-pcie"
12
13
 - reg: base address and length of the PCIe controller
13
14
 - interrupts: A list of interrupt outputs of the controller. Must contain an
14
15
   entry for each entry in the interrupt-names property.
..
..
@@ -41,15 +42,23 @@
41
42
 Additional required properties for imx6sx-pcie:
42
43
 - clock names: Must include the following additional entries:
43
44
 	- "pcie_inbound_axi"
44
-- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain
45
+- power-domains: Must be set to phandles pointing to the DISPLAY and
46
+  PCIE_PHY power domains
47
+- power-domain-names: Must be "pcie", "pcie_phy"
45
48
 
46
-Additional required properties for imx7d-pcie:
49
+Additional required properties for imx7d-pcie and imx8mq-pcie:
47
50
 - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
48
51
 - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
49
52
   IP block
50
-- reset-names: Must contain the following entires:
53
+- reset-names: Must contain the following entries:
51
54
 	       - "pciephy"
52
55
 	       - "apps"
56
+	       - "turnoff"
57
+- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
58
+
59
+Additional required properties for imx8mq-pcie:
60
+- clock-names: Must include the following additional entries:
61
+	- "pcie_aux"
53
62
 
54
63
 Example:
55
64
 
..
..
@@ -76,3 +85,13 @@
76
85
 		clocks = <&clks 144>, <&clks 206>, <&clks 189>;
77
86
 		clock-names = "pcie", "pcie_bus", "pcie_phy";
78
87
 	};
88
+
89
+* Freescale i.MX7d PCIe PHY
90
+
91
+This is the PHY associated with the IMX7d PCIe controller.  It's used by the
92
+PCI-e controller via the fsl,imx7d-pcie-phy phandle.
93
+
94
+Required properties:
95
+- compatible:
96
+	- "fsl,imx7d-pcie-phy"
97
+- reg: base address and length of the PCIe PHY controller