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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
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@@ -4,15 +4,38 @@
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 and the properties used by the sdhci-msm driver.
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 Required properties:
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-- compatible: Should contain:
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+- compatible: Should contain a SoC-specific string and a IP version string:
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+	version strings:
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 		"qcom,sdhci-msm-v4" for sdcc versions less than 5.0
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-		"qcom,sdhci-msm-v5" for sdcc versions >= 5.0
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+		"qcom,sdhci-msm-v5" for sdcc version 5.0
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 		For SDCC version 5.0.0, MCI registers are removed from SDCC
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 		interface and some registers are moved to HC. New compatible
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 		string is added to support this change - "qcom,sdhci-msm-v5".
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+	full compatible strings with SoC and version:
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+		"qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
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+		"qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
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+		"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
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+		"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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+		"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
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+		"qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
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+		"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
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+		"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
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+		"qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
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+	NOTE that some old device tree files may be floating around that only
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+	have the string "qcom,sdhci-msm-v4" without the SoC compatible string
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+	but doing that should be considered a deprecated practice.
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+
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 - reg: Base address and length of the register in the following order:
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 	- Host controller register map (required)
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-	- SD Core register map (required)
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+	- SD Core register map (required for controllers earlier than msm-v5)
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+	- CQE register map (Optional, CQE support is present on SDHC instance meant
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+	                    for eMMC and version v4.2 and above)
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+	- Inline Crypto Engine register map (optional)
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+- reg-names: When CQE register map is supplied, below reg-names are required
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+	- "hc" for Host controller register map
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+	- "core" for SD core register map
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+	- "cqhci" for CQE register map
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+	- "ice" for Inline Crypto Engine register map (optional)
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 - interrupts: Should contain an interrupt-specifiers for the interrupts:
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 	- Host controller interrupt (required)
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 - pinctrl-names: Should contain only one value - "default".
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@@ -25,11 +48,34 @@
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 	"xo"	- TCXO clock (optional)
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 	"cal"	- reference clock for RCLK delay calibration (optional)
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 	"sleep"	- sleep clock for RCLK delay calibration (optional)
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+	"ice" - clock for Inline Crypto Engine (optional)
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+
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+- qcom,ddr-config: Certain chipsets and platforms require particular settings
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+	for the DDR_CONFIG register. Use this field to specify the register
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+	value as per the Hardware Programming Guide.
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+
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+- qcom,dll-config: Chipset and Platform specific value. Use this field to
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+	specify the DLL_CONFIG register value as per Hardware Programming Guide.
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+
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+Optional Properties:
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+* Following bus parameters are required for interconnect bandwidth scaling:
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+- interconnects: Pairs of phandles and interconnect provider specifier
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+		 to denote the edge source and destination ports of
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+		 the interconnect path.
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+
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+- interconnect-names: For sdhc, we have two main paths.
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+		1. Data path : sdhc to ddr
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+		2. Config path : cpu to sdhc
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+		For Data interconnect path the name supposed to be
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+		is "sdhc-ddr" and for config interconnect path it is
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+		"cpu-sdhc".
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+		Please refer to Documentation/devicetree/bindings/
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+		interconnect/ for more details.
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 Example:
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 	sdhc_1: sdhci@f9824900 {
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-		compatible = "qcom,sdhci-msm-v4";
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+		compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
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 		reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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 		interrupts = <0 123 0>;
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 		bus-width = <8>;
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@@ -43,10 +89,16 @@
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 		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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 		clock-names = "core", "iface";
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+		interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
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+				<&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
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+		interconnect-names = "sdhc-ddr","cpu-sdhc";
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+
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+		qcom,dll-config = <0x000f642c>;
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+		qcom,ddr-config = <0x80040868>;
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 	};
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 	sdhc_2: sdhci@f98a4900 {
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-		compatible = "qcom,sdhci-msm-v4";
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+		compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
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 		reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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 		interrupts = <0 125 0>;
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 		bus-width = <4>;
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@@ -60,4 +112,7 @@
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 		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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 		clock-names = "core", "iface";
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+
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+		qcom,dll-config = <0x0007642c>;
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+		qcom,ddr-config = <0x80040868>;
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 	};