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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
....@@ -14,8 +14,16 @@
1414   - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
1515   - "nvidia,tegra210-sdhci": for Tegra210
1616   - "nvidia,tegra186-sdhci": for Tegra186
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-- clocks : Must contain one entry, for the module clock.
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-  See ../clocks/clock-bindings.txt for details.
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+  - "nvidia,tegra194-sdhci": for Tegra194
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+- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
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+	  One for the module clock and one for the timeout clock.
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+	  For all other Tegra devices, must contain a single entry for
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+	  the module clock. See ../clocks/clock-bindings.txt for details.
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+- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
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+	       strings 'sdhci' and 'tmclk' to represent the module and
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+	       the timeout clocks, respectively.
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+	       For all other Tegra devices must contain the string 'sdhci'
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+	       to represent the module clock.
1927 - resets : Must contain an entry for each entry in reset-names.
2028   See ../reset/reset.txt for details.
2129 - reset-names : Must include the following entries:
....@@ -38,3 +46,98 @@
3846 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
3947 	bus-width = <8>;
4048 };
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+
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+Optional properties for Tegra210, Tegra186 and Tegra194:
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+- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
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+  configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
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+  for controllers supporting multiple voltage levels. The order of names
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+  should correspond to the pin configuration states in pinctrl-0 and
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+  pinctrl-1.
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+- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
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+  Tegra210 where pad config registers are in the pinmux register domain
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+  for pull-up-strength and pull-down-strength values configuration when
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+  using pads at 3V3 and 1V8 levels.
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+- nvidia,only-1-8-v : The presence of this property indicates that the
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+  controller operates at a 1.8 V fixed I/O voltage.
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+- nvidia,pad-autocal-pull-up-offset-3v3,
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+  nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
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+  calibration offsets for 3.3 V signaling modes.
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+- nvidia,pad-autocal-pull-up-offset-1v8,
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+  nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
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+  calibration offsets for 1.8 V signaling modes.
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+- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
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+  nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
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+  strength used as a fallback in case the automatic calibration times
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+  out on a 3.3 V signaling mode.
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+- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
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+  nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
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+  strength used as a fallback in case the automatic calibration times
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+  out on a 1.8 V signaling mode.
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+- nvidia,pad-autocal-pull-up-offset-sdr104,
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+  nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
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+  calibration offsets for SDR104 mode.
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+- nvidia,pad-autocal-pull-up-offset-hs400,
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+  nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
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+  calibration offsets for HS400 mode.
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+- nvidia,default-tap : Specify the default inbound sampling clock
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+  trimmer value for non-tunable modes.
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+- nvidia,default-trim : Specify the default outbound clock trimmer
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+  value.
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+- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
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+
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+  Notes on the pad calibration pull up and pulldown offset values:
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+    - The property values are drive codes which are programmed into the
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+      PD_OFFSET and PU_OFFSET sections of the
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+      SDHCI_TEGRA_AUTO_CAL_CONFIG register.
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+    - A higher value corresponds to higher drive strength. Please refer
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+      to the reference manual of the SoC for correct values.
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+    - The SDR104 and HS400 timing specific values are used in
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+      corresponding modes if specified.
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+
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+  Notes on tap and trim values:
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+    - The values are used for compensating trace length differences
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+      by adjusting the sampling point.
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+    - The values are programmed to the Vendor Clock Control Register.
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+      Please refer to the reference manual of the SoC for correct
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+      values.
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+    - The DQS trim values are only used on controllers which support
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+      HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
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+      HS400.
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+
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+Example:
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+sdhci@700b0000 {
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+	compatible = "nvidia,tegra124-sdhci";
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+	reg = <0x0 0x700b0000 0x0 0x200>;
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+	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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+	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
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+	clock-names = "sdhci";
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+	resets = <&tegra_car 14>;
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+	reset-names = "sdhci";
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+	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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+	pinctrl-0 = <&sdmmc1_3v3>;
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+	pinctrl-1 = <&sdmmc1_1v8>;
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+	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
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+	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
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+	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
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+	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
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+	status = "disabled";
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+};
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+
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+sdhci@700b0000 {
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+	compatible = "nvidia,tegra210-sdhci";
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+	reg = <0x0 0x700b0000 0x0 0x200>;
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+	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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+	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
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+		 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
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+	clock-names = "sdhci", "tmclk";
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+	resets = <&tegra_car 14>;
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+	reset-names = "sdhci";
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+	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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+	pinctrl-0 = <&sdmmc1_3v3>;
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+	pinctrl-1 = <&sdmmc1_1v8>;
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+	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
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+	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
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+	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
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+	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
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+	status = "disabled";
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+};