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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/mmc/mtk-sd.txt
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@@ -10,10 +10,14 @@
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 - compatible: value should be either of the following.
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 	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
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 	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
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+	"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
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+	"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
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+	"mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
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 	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
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 	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
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 	"mediatek,mt7622-mmc": for MT7622 SoC
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 	"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
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+	"mediatek,mt7620-mmc", for MT7621 SoC (and others)
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 - reg: physical base address of the controller and length
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 - interrupts: Should contain MSDC interrupt number
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@@ -22,6 +26,7 @@
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 	"source" - source clock (required)
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 	"hclk" - HCLK which used for host (required)
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 	"source_cg" - independent source clock gate (required for MT2712)
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+	"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
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 - pinctrl-names: should be "default", "state_uhs"
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 - pinctrl-0: should contain default/high speed pin ctrl
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 - pinctrl-1: should contain uhs mode pin ctrl
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@@ -45,6 +50,8 @@
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 		     error caused by stop clock(fifo full)
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 		     Valid range = [0:0x7]. if not present, default value is 0.
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 		     applied to compatible "mediatek,mt2701-mmc".
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+- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
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+- reset-names: Should be "hrst".
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 Examples:
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 mmc0: mmc@11230000 {