.. | .. |
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15 | 15 | Optional properties: |
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16 | 16 | - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides |
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17 | 17 | the ID provided by the HW |
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| 18 | +- resets : phandle to internal reset line. |
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| 19 | + Should be defined for sdmmc variant. |
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18 | 20 | - vqmmc-supply : phandle to the regulator device tree node, mentioned |
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19 | 21 | as the VCCQ/VDD_IO supply in the eMMC/SD specs. |
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| 22 | +specific for ux500 variant: |
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20 | 23 | - st,sig-dir-dat0 : bus signal direction pin used for DAT[0]. |
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21 | 24 | - st,sig-dir-dat2 : bus signal direction pin used for DAT[2]. |
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22 | 25 | - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1]. |
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.. | .. |
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24 | 27 | - st,sig-dir-cmd : cmd signal direction pin used for CMD. |
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25 | 28 | - st,sig-pin-fbclk : feedback clock signal pin used. |
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26 | 29 | |
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| 30 | +specific for sdmmc variant: |
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| 31 | +- reg : a second base register may be defined if a delay |
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| 32 | + block is present and used for tuning. |
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| 33 | +- st,sig-dir : signal direction polarity used for cmd, dat0 dat123. |
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| 34 | +- st,neg-edge : data & command phase relation, generated on |
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| 35 | + sd clock falling edge. |
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| 36 | +- st,use-ckin : use ckin pin from an external driver to sample |
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| 37 | + the receive data (example: with voltage |
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| 38 | + switch transceiver). |
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| 39 | + |
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27 | 40 | Deprecated properties: |
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28 | 41 | - mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable. |
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29 | 42 | - mmc-cap-sd-highspeed : indicates whether SD is high speed capable. |
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