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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
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@@ -9,11 +9,9 @@
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   See ../clocks/clock-bindings.txt for details.
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 - clock-names: Must include the following entries:
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   - cpu_g: Clock mux for the fast CPU cluster.
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-  - cpu_lp: Clock mux for the low-power CPU cluster.
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   - pll_x: Fast PLL clocksource.
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   - pll_p: Auxiliary PLL used during fast PLL rate changes.
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   - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
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-- vdd-cpu-supply: Regulator for CPU voltage
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 Optional properties:
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 - clock-latency: Specify the possible maximum transition latency for clock,
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@@ -31,13 +29,11 @@
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 		reg = <0>;
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 		clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
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-			 <&tegra_car TEGRA124_CLK_CCLK_LP>,
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 			 <&tegra_car TEGRA124_CLK_PLL_X>,
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 			 <&tegra_car TEGRA124_CLK_PLL_P>,
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 			 <&dfll>;
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-		clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
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+		clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
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 		clock-latency = <300000>;
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-		vdd-cpu-supply: <&vdd_cpu>;
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 	};
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 	<...>