.. | .. |
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28 | 28 | * "fsl,p4080-clockgen" |
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29 | 29 | * "fsl,p5020-clockgen" |
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30 | 30 | * "fsl,p5040-clockgen" |
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| 31 | + * "fsl,t1023-clockgen" |
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| 32 | + * "fsl,t1024-clockgen" |
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| 33 | + * "fsl,t1040-clockgen" |
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| 34 | + * "fsl,t1042-clockgen" |
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| 35 | + * "fsl,t2080-clockgen" |
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| 36 | + * "fsl,t2081-clockgen" |
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31 | 37 | * "fsl,t4240-clockgen" |
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32 | 38 | * "fsl,b4420-clockgen" |
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33 | 39 | * "fsl,b4860-clockgen" |
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34 | 40 | * "fsl,ls1012a-clockgen" |
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35 | 41 | * "fsl,ls1021a-clockgen" |
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| 42 | + * "fsl,ls1028a-clockgen" |
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36 | 43 | * "fsl,ls1043a-clockgen" |
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37 | 44 | * "fsl,ls1046a-clockgen" |
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38 | 45 | * "fsl,ls1088a-clockgen" |
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.. | .. |
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77 | 84 | 1 cmux index (n in CLKCnCSR) |
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78 | 85 | 2 hwaccel index (n in CLKCGnHWACSR) |
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79 | 86 | 3 fman 0 for fm1, 1 for fm2 |
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80 | | - 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 |
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81 | | - 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 |
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| 87 | + 4 platform pll n=pll/(n+1). For example, when n=1, |
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| 88 | + that means output_freq=PLL_freq/2. |
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82 | 89 | 5 coreclk must be 0 |
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83 | 90 | |
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84 | 91 | 3. Example |
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