移去rt

hc

2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
..
..
@@ -8,10 +8,11 @@
8
8
 oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
9
9
 control module that will automatically adjust the VDD_CPU voltage by
10
10
 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
11
-Currently only the I2C mode is supported by these bindings.
12
11
 
13
12
 Required properties:
14
-- compatible : should be "nvidia,tegra124-dfll"
13
+- compatible : should be one of:
14
+  - "nvidia,tegra124-dfll": for Tegra124
15
+  - "nvidia,tegra210-dfll": for Tegra210
15
16
 - reg : Defines the following set of registers, in the order listed:
16
17
         - registers for the DFLL control logic.
17
18
         - registers for the I2C output logic.
..
..
@@ -45,10 +46,31 @@
45
46
 Optional properties for the control loop parameters:
46
47
 - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
47
48
 
49
+Optional properties for mode selection:
50
+- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
51
+
48
52
 Required properties for I2C mode:
49
53
 - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
50
54
 
51
-Example:
55
+Required properties for PWM mode:
56
+- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
57
+- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
58
+  control is disabled and the PWM output is tristated. Note that this voltage is
59
+  configured in hardware, typically via a resistor divider.
60
+- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
61
+  is enabled and PWM output is low. Hence, this is the minimum output voltage
62
+  that the regulator supports when PWM control is enabled.
63
+- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
64
+  corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
65
+  duty cycle would be: nvidia,pwm-min-microvolts +
66
+  nvidia,pwm-voltage-step-microvolts * 2.
67
+- pinctrl-0: I/O pad configuration when PWM control is enabled.
68
+- pinctrl-1: I/O pad configuration when PWM control is disabled.
69
+- pinctrl-names: must include the following entries:
70
+  - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
71
+  - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
72
+
73
+Example for I2C:
52
74
 
53
75
 clock@70110000 {
54
76
         compatible = "nvidia,tegra124-dfll";
..
..
@@ -76,3 +98,58 @@
76
98
 
77
99
         nvidia,i2c-fs-rate = <400000>;
78
100
 };
101
+
102
+Example for PWM:
103
+
104
+clock@70110000 {
105
+	compatible = "nvidia,tegra124-dfll";
106
+	reg = <0 0x70110000 0 0x100>, /* DFLL control */
107
+	      <0 0x70110000 0 0x100>, /* I2C output control */
108
+	      <0 0x70110100 0 0x100>, /* Integrated I2C controller */
109
+	      <0 0x70110200 0 0x100>; /* Look-up table RAM */
110
+	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
111
+	clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
112
+	         <&tegra_car TEGRA210_CLK_DFLL_REF>,
113
+		 <&tegra_car TEGRA124_CLK_I2C5>;;
114
+	clock-names = "soc", "ref", "i2c";
115
+	resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
116
+	reset-names = "dvco";
117
+	#clock-cells = <0>;
118
+	clock-output-names = "dfllCPU_out";
119
+
120
+	nvidia,sample-rate = <25000>;
121
+	nvidia,droop-ctrl = <0x00000f00>;
122
+	nvidia,force-mode = <1>;
123
+	nvidia,cf = <6>;
124
+	nvidia,ci = <0>;
125
+	nvidia,cg = <2>;
126
+
127
+	nvidia,pwm-min-microvolts = <708000>; /* 708mV */
128
+	nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
129
+	nvidia,pwm-to-pmic;
130
+	nvidia,pwm-tristate-microvolts = <1000000>;
131
+	nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
132
+
133
+	pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
134
+	pinctrl-0 = <&dvfs_pwm_active_state>;
135
+	pinctrl-1 = <&dvfs_pwm_inactive_state>;
136
+};
137
+
138
+/* pinmux nodes added for completeness. Binding doc can be found in:
139
+ * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
140
+ */
141
+
142
+pinmux: pinmux@700008d4 {
143
+	dvfs_pwm_active_state: dvfs_pwm_active {
144
+		dvfs_pwm_pbb1 {
145
+			nvidia,pins = "dvfs_pwm_pbb1";
146
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
147
+		};
148
+	};
149
+	dvfs_pwm_inactive_state: dvfs_pwm_inactive {
150
+		dvfs_pwm_pbb1 {
151
+			nvidia,pins = "dvfs_pwm_pbb1";
152
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
153
+		};
154
+	};
155
+};