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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
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@@ -50,6 +50,8 @@
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     IPs.
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   - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
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     which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
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+  - "samsung,exynos5433-cmu-imem"   - clock controller compatible for CMU_IMEM
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+    which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
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 - reg: physical base address of the controller and length of memory mapped
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   region.
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@@ -167,6 +169,12 @@
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 		- aclk_cam1_333
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 		- aclk_cam1_400
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 		- aclk_cam1_552
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+
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+	Input clocks for imem clock controller:
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+		- oscclk
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+		- aclk_imem_sssx_266
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+		- aclk_imem_266
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+		- aclk_imem_200
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 Optional properties:
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   - power-domains: a phandle to respective power domain node as described by
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@@ -469,6 +477,21 @@
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 		power-domains = <&pd_cam1>;
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 	};
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+	cmu_imem: clock-controller@11060000 {
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+		compatible = "samsung,exynos5433-cmu-imem";
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+		reg = <0x11060000 0x1000>;
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+		#clock-cells = <1>;
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+
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+		clock-names = "oscclk",
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+			"aclk_imem_sssx_266",
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+			"aclk_imem_266",
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+			"aclk_imem_200";
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+		clocks = <&xxti>,
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+			<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
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+			<&cmu_top CLK_DIV_ACLK_IMEM_266>,
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+			<&cmu_top CLK_DIV_ACLK_IMEM_200>;
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+	};
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+
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 Example 3: UART controller node that consumes the clock generated by the clock
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 	   controller.
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