/*
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* Copyright (C) 2001 by Hiroyuki Kondo
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*/
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#define M32R_MAX_PCC 2
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/*
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* M32R PC Card Controller
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*/
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#define M32R_PCC0_BASE 0x00ef7000
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#define M32R_PCC1_BASE 0x00ef7020
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/*
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* Register offsets
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*/
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#define PCCR 0x00
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#define PCADR 0x04
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#define PCMOD 0x08
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#define PCIRC 0x0c
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#define PCCSIGCR 0x10
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#define PCATCR 0x14
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/*
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* PCCR
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*/
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#define PCCR_PCEN (1UL<<(31-31))
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/*
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* PCIRC
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*/
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#define PCIRC_BWERR (1UL<<(31-7))
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#define PCIRC_CDIN1 (1UL<<(31-14))
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#define PCIRC_CDIN2 (1UL<<(31-15))
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#define PCIRC_BEIEN (1UL<<(31-23))
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#define PCIRC_CIIEN (1UL<<(31-30))
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#define PCIRC_COIEN (1UL<<(31-31))
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/*
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* PCCSIGCR
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*/
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#define PCCSIGCR_SEN (1UL<<(31-3))
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#define PCCSIGCR_VEN (1UL<<(31-7))
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#define PCCSIGCR_CRST (1UL<<(31-15))
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#define PCCSIGCR_COCR (1UL<<(31-31))
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/*
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*
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*/
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#define PCMOD_AS_ATTRIB (1UL<<(31-19))
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#define PCMOD_AS_IO (1UL<<(31-18))
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#define PCMOD_CBSZ (1UL<<(31-23)) /* set for 8bit */
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#define PCMOD_DBEX (1UL<<(31-31)) /* set for excahnge */
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/*
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* M32R PCC Map addr
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*/
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#define M32R_PCC0_MAPBASE 0x14000000
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#define M32R_PCC1_MAPBASE 0x16000000
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#define M32R_PCC_MAPMAX 0x02000000
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#define M32R_PCC_MAPSIZE 0x00001000 /* XXX */
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#define M32R_PCC_MAPMASK (~(M32R_PCC_MAPMAX-1))
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