/*
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* arch/arm64/include/asm/arch_timer.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_TIMER_H
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#define __ASM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <asm/sysreg.h>
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/jump_label.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
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extern struct static_key_false arch_timer_read_ool_enabled;
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#define needs_fsl_a008585_workaround() \
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static_branch_unlikely(&arch_timer_read_ool_enabled)
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#else
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#define needs_fsl_a008585_workaround() false
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#endif
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u32 __fsl_a008585_read_cntp_tval_el0(void);
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u32 __fsl_a008585_read_cntv_tval_el0(void);
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u64 __fsl_a008585_read_cntvct_el0(void);
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/*
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* The number of retries is an arbitrary value well beyond the highest number
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* of iterations the loop has been observed to take.
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*/
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#define __fsl_a008585_read_reg(reg) ({ \
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u64 _old, _new; \
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int _retries = 200; \
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\
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do { \
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_old = read_sysreg(reg); \
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_new = read_sysreg(reg); \
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_retries--; \
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} while (unlikely(_old != _new) && _retries); \
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\
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WARN_ON_ONCE(!_retries); \
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_new; \
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})
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#define arch_timer_reg_read_stable(reg) \
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({ \
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u64 _val; \
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if (needs_fsl_a008585_workaround()) \
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_val = __fsl_a008585_read_##reg(); \
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else \
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_val = read_sysreg(reg); \
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_val; \
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})
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code.
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntp_ctl_el0);
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break;
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case ARCH_TIMER_REG_TVAL:
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write_sysreg(val, cntp_tval_el0);
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntv_ctl_el0);
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break;
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case ARCH_TIMER_REG_TVAL:
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write_sysreg(val, cntv_tval_el0);
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break;
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}
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}
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isb();
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}
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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return read_sysreg(cntp_ctl_el0);
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case ARCH_TIMER_REG_TVAL:
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return arch_timer_reg_read_stable(cntp_tval_el0);
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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return read_sysreg(cntv_ctl_el0);
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case ARCH_TIMER_REG_TVAL:
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return arch_timer_reg_read_stable(cntv_tval_el0);
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}
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}
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BUG();
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}
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static __always_inline
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u64 arch_timer_reg_read_cval(int access)
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{
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u64 cval;
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if (access == ARCH_TIMER_PHYS_ACCESS)
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asm volatile("mrs %0, cntp_cval_el0" : "=r" (cval));
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else if (access == ARCH_TIMER_VIRT_ACCESS)
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asm volatile("mrs %0, cntv_cval_el0" : "=r" (cval));
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else
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cval = 0;
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return cval;
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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return read_sysreg(cntfrq_el0);
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}
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static inline u32 arch_timer_get_cntkctl(void)
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{
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return read_sysreg(cntkctl_el1);
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}
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static inline void arch_timer_set_cntkctl(u32 cntkctl)
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{
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write_sysreg(cntkctl, cntkctl_el1);
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}
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#if defined(CONFIG_ARCH_SUN50IW1P1) \
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|| defined(CONFIG_ARCH_SUN50IW2P1)
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#define ARCH_PCNT_TRY_MAX_TIME (12)
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#define ARCH_PCNT_MAX_DELTA (8)
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static inline u64 arch_counter_get_cntpct(void)
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{
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u64 pct0;
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u64 pct1;
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u64 delta;
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u32 retry = 0;
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/* sun50i vcnt maybe imprecise,
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* we should try to fix this.
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*/
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while (retry < ARCH_PCNT_TRY_MAX_TIME) {
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isb();
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asm volatile("mrs %0, cntvct_el0" : "=r" (pct0));
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isb();
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asm volatile("mrs %0, cntvct_el0" : "=r" (pct1));
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delta = pct1 - pct0;
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if ((pct1 >= pct0) && (delta < ARCH_PCNT_MAX_DELTA)) {
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/* read valid vcnt */
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return pct1;
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}
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/* vcnt value error, try again */
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retry++;
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}
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/* Do not warry for this, just return the last time vcnt.
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* arm64 have enabled CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE.
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*/
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return pct1;
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}
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#else
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static inline u64 arch_counter_get_cntpct(void)
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{
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/*
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* AArch64 kernel and user space mandate the use of CNTVCT.
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*/
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BUG();
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return 0;
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}
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#endif
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#if defined(CONFIG_ARCH_SUN50IW1P1) \
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|| defined(CONFIG_ARCH_SUN50IW2P1)
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#define ARCH_VCNT_TRY_MAX_TIME (12)
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#define ARCH_VCNT_MAX_DELTA (8)
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static inline u64 arch_counter_get_cntvct(void)
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{
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u64 vct0;
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u64 vct1;
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u64 delta;
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u32 retry = 0;
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/* sun50i vcnt maybe imprecise,
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* we should try to fix this.
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*/
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while (retry < ARCH_VCNT_TRY_MAX_TIME) {
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isb();
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asm volatile("mrs %0, cntvct_el0" : "=r" (vct0));
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isb();
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asm volatile("mrs %0, cntvct_el0" : "=r" (vct1));
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delta = vct1 - vct0;
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if ((vct1 >= vct0) && (delta < ARCH_VCNT_MAX_DELTA)) {
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/* read valid vcnt */
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return vct1;
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}
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/* vcnt value error, try again */
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retry++;
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}
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/* Do not warry for this, just return the last time vcnt.
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* arm64 have enabled CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE.
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*/
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return vct1;
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}
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#else
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static inline u64 arch_counter_get_cntvct(void)
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{
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isb();
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return arch_timer_reg_read_stable(cntvct_el0);
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}
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#endif
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static inline int arch_timer_arch_init(void)
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{
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return 0;
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}
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#endif
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