// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some board init for the Allwinner A10-evb board.
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*/
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#include <common.h>
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#include <mmc.h>
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#include <axp_pmic.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/display.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/usb_phy.h>
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#ifndef CONFIG_ARM64
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#include <asm/armv7.h>
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#endif
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <crc.h>
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#include <environment.h>
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#include <linux/libfdt.h>
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#include <nand.h>
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#include <net.h>
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#include <spl.h>
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#include <sy8106a.h>
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#include <asm/setup.h>
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#include <private_uboot.h>
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#include <sunxi_board.h>
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#ifdef CONFIG_SUNXI_POWER
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#include <sunxi_power/axp.h>
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#include <sunxi_power/power_manage.h>
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#endif
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#ifdef CONFIG_SUNXI_DMA
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#include <asm/arch/dma.h>
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#endif
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#include <mapmem.h>
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int __attribute__((weak)) sunxi_set_sramc_mode(void)
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{
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return 0;
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}
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int __attribute__((weak)) clock_set_corepll(int frequency)
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{
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return 0;
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}
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SUNXI_OVERLAY
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__weak int sunxi_overlay_apply_merged(void *dtb_base, void *dtbo_base)
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{
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return fdt_check_header(dtbo_base);
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}
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#endif
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void i2c_init_board(void)
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{
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__maybe_unused char fdt_node_str[8] = {0};
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#ifdef CONFIG_I2C0_ENABLE
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#if defined(CONFIG_MACH_SUN8IW18)
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#if 0 /*twi0 & uart0 use the same pin*/
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sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN8I_GPH_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN8I_GPH_TWI0);
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clock_twi_onoff(0,1);
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#endif
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#else
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sprintf(fdt_node_str, "twi0");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#endif
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#ifdef CONFIG_I2C1_ENABLE
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#if defined(CONFIG_MACH_SUN8IW18)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI1);
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/*clock_twi_onoff(1, 1);*/
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#else
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sprintf(fdt_node_str, "twi1");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#endif
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#ifdef CONFIG_I2C2_ENABLE
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sprintf(fdt_node_str, "twi2");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#ifdef CONFIG_I2C3_ENABLE
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sprintf(fdt_node_str, "twi3");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#ifdef CONFIG_I2C4_ENABLE
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sprintf(fdt_node_str, "twi4");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#ifdef CONFIG_I2C5_ENABLE
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sprintf(fdt_node_str, "twi5");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#ifdef CONFIG_R_I2C0_ENABLE
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#if defined(CONFIG_MACH_SUN50IW11)
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sunxi_gpio_set_cfgpin(SUNXI_GPL(5), SUN8I_H3_GPL_R_TWI);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUN8I_H3_GPL_R_TWI);
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#else
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#if defined(CONFIG_MACH_SUN50IW9)
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sprintf(fdt_node_str, "twi5");
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#elif defined(CONFIG_MACH_SUN50IW10)
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sprintf(fdt_node_str, "twi6");
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#else
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sprintf(fdt_node_str, "twi4");
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#endif
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#ifdef CONFIG_R_I2C1_ENABLE
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sprintf(fdt_node_str, "twi7");
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fdt_set_all_pin(fdt_node_str, "pinctrl-0");
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#endif
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#endif
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}
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void enable_smp(void)
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{
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/* SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg:ACTLR */
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asm volatile("MRC p15, 0, r0, c1, c0, 1");
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asm volatile("ORR r0, r0, #0x040");
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asm volatile("MCR p15, 0, r0, c1, c0, 1");
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}
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void smp_init(void)
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{
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int cpu_status = 0;
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#if CONFIG_SUNXI_NCAT
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cpu_status = readl(SUNXI_CPUXCFG_BASE+0x80);
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cpu_status &= (0xf<<24);
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#else
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/*old platform enable smp unconditionally*/
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cpu_status = 1;
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#endif
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/* note:
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sbrom will enable smp bit when jmp to non-secure fel.
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but normal brom not do this operation.
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so should enable smp when run uboot by normal fel mode.
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*/
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if(!cpu_status)
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enable_smp();
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}
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int sunxi_plat_init(void)
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{
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sunxi_probe_securemode();
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#ifdef CONFIG_SUNXI_DMA
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sunxi_dma_init();
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#endif
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#ifdef CONFIG_SUNXI_ARISC_EXIST
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sunxi_arisc_probe();
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#endif
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return 0;
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}
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/* add board specific code here */
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int board_init(void)
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{
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__maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
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gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
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sunxi_plat_init();
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int work_mode = get_boot_work_mode();
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ret = axp_gpio_init();
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if (ret)
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return ret;
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#ifdef CONFIG_SUNXI_POWER
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if (!axp_probe()) {
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axp_set_dcdc_mode();
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axp_set_power_supply_output();
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#if defined CONFIG_SUNXI_BMU && !defined CONFIG_AXP_LATE_INFO
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gd->pmu_saved_status = bmu_get_poweron_source();
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gd->pmu_runtime_chgcur = axp_get_battery_status();
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if (work_mode != WORK_MODE_BOOT) {
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ret = axp_reset_capacity();
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if (!ret) {
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pr_msg("axp reset capacity fail!\n");
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}
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}
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#else
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gd->pmu_saved_status = -1;
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#endif
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}
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#endif
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if ((work_mode == WORK_MODE_BOOT) ||
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(work_mode == WORK_MODE_CARD_PRODUCT) ||
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(work_mode == WORK_MODE_CARD_UPDATE))
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sunxi_set_sramc_mode();
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clock_set_corepll(uboot_spare_head.boot_data.run_clock);
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tick_printf("CPU=%d MHz,PLL6=%d Mhz,AHB=%d Mhz, APB1=%dMhz MBus=%dMhz\n",
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clock_get_corepll(),
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clock_get_pll6(), clock_get_ahb(),
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clock_get_apb1(),clock_get_mbus());
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return 0;
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}
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int dram_init(void)
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{
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uint dram_size = 0;
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dram_size = uboot_spare_head.boot_data.dram_scan_size;
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dram_size = dram_size > 2048 ? 2048 : dram_size;
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if(dram_size)
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gd->ram_size = dram_size * 1024 * 1024;
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else
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
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return 0;
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}
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#ifdef CONFIG_MMC
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static void mmc_pinmux_setup(int sdc)
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{
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#if 0
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unsigned int pin;
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__maybe_unused int pins;
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switch (sdc) {
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case 0:
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/* SDC0: PF0-PF5 */
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for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 2:
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pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
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#if defined(CONFIG_MACH_SUN50IW6)
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/* SDC2: PC4-PC14 */
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for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#endif
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break;
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default:
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printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
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break;
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}
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#endif
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}
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/*
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int board_mmc_init(bd_t *bis)
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{
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sunxi_mmc_init(bis->bi_card_num);
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return 0;
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}
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*/
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void board_mmc_pre_init(int card_num)
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{
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bd_t *bd;
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bd = gd->bd;
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//gd->bd->bi_card_num = card_num;
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mmc_initialize(bd);
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}
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int board_mmc_get_num(void)
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{
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return gd->boot_card_num;
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}
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void board_mmc_set_num(int num)
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{
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gd->boot_card_num = num;
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}
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int board_mmc_init(bd_t *bis)
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{
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__maybe_unused struct mmc *mmc0, *mmc1;
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__maybe_unused char buf[512];
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mmc_pinmux_setup(board_mmc_get_num());
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mmc0 = sunxi_mmc_init(board_mmc_get_num());
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if (!mmc0)
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return -1;
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#if 0
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#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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if (!mmc1)
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return -1;
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#endif
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_GADGET
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int g_dnl_board_usb_cable_connected(void)
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{
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return sunxi_usb_phy_vbus_detect(0);
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}
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#endif
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/*
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* Note this function gets called multiple times.
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* It must not make any changes to env variables which already exist.
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*/
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static void setup_environment(const void *fdt)
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{
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#ifdef CONFIG_USB
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__maybe_unused unsigned int sid[4];
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__maybe_unused uint8_t mac_addr[6];
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__maybe_unused char ethaddr[16];
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__maybe_unused int ret;
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ret = sunxi_get_sid(sid);
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if (ret == 0 && sid[0] != 0) {
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/*
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* The single words 1 - 3 of the SID have quite a few bits
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* which are the same on many models, so we take a crc32
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* of all 3 words, to get a more unique value.
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*
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* Note we only do this on newer SoCs as we cannot change
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* the algorithm on older SoCs since those have been using
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* fixed mac-addresses based on only using word 3 for a
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* long time and changing a fixed mac-address with an
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* u-boot update is not good.
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*/
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sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
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/* Ensure the NIC specific bytes of the mac are not all 0 */
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if ((sid[3] & 0xffffff) == 0)
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sid[3] |= 0x800000;
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strcpy(ethaddr, "ethaddr");
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/* Non OUI / registered MAC address */
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mac_addr[0] = (0 << 4) | 0x02;
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mac_addr[1] = (sid[0] >> 0) & 0xff;
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mac_addr[2] = (sid[3] >> 24) & 0xff;
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mac_addr[3] = (sid[3] >> 16) & 0xff;
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mac_addr[4] = (sid[3] >> 8) & 0xff;
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mac_addr[5] = (sid[3] >> 0) & 0xff;
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eth_env_set_enetaddr(ethaddr, mac_addr);
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}
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#endif
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}
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int misc_init_r(void)
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{
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__maybe_unused int ret;
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setup_environment(gd->fdt_blob);
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#if 0
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ret = sunxi_usb_phy_probe();
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if (ret)
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return ret;
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#endif
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#ifdef CONFIG_USB_ETHER
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usb_ether_init();
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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int __maybe_unused r;
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/*
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* Call setup_environment again in case the boot fdt has
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* ethernet aliases the u-boot copy does not have.
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*/
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setup_environment(blob);
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#ifdef CONFIG_VIDEO_DT_SIMPLEFB
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r = sunxi_simplefb_setup(blob);
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if (r)
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return r;
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#endif
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return 0;
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}
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static int reserve_bootlogo(void)
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{
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uint32_t *compressed_logo_size =
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(uint32_t *)(CONFIG_SYS_TEXT_BASE + (3 * 1024 * 1024));
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uint32_t *compressed_logo_buf =
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(uint32_t *)(CONFIG_SYS_TEXT_BASE + (3 * 1024 * 1024) + 16);
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gd->boot_logo_addr = 0;
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if (get_boot_work_mode() != WORK_MODE_BOOT) {
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debug("no boot mode, dont read bootlogo\n");
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return 0;
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}
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if (((uboot_spare_head.boot_data.func_mask &
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UBOOT_FUNC_MASK_BIT_BOOTLOGO) != UBOOT_FUNC_MASK_BIT_BOOTLOGO) ||
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(*compressed_logo_size == 0)) {
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debug("no bootlogo from boot_package\n");
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return 0;
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}
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gd->start_addr_sp -= ALIGN(*compressed_logo_size, 16);
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gd->boot_logo_addr =
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(ulong)map_sysmem(gd->start_addr_sp, *compressed_logo_size);
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memcpy((void *)gd->boot_logo_addr, compressed_logo_buf,
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*compressed_logo_size);
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debug("reserve: 0x%lx from 0x%x: for boot logo in boot package\n",
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gd->boot_logo_addr, *compressed_logo_size);
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return 0;
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}
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int reserve_arch(void)
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{
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reserve_bootlogo();
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return 0;
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}
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