// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <power/pmic.h>
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#include <power/stpmu1.h>
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#ifdef CONFIG_PMIC_STPMU1
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int board_ddr_power_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_GET_DRIVER(pmic_stpmu1), &dev);
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if (ret)
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/* No PMIC on board */
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return 0;
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/* Set LDO3 to sync mode */
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ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMU1_LDO3_MODE;
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ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
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ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
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ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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/* Set BUCK2 to 1.35V */
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ret = pmic_clrsetbits(dev,
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STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
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STPMU1_BUCK_OUTPUT_MASK,
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STPMU1_BUCK2_1350000V);
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if (ret < 0)
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return ret;
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/* Enable BUCK2 and VREF */
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ret = pmic_clrsetbits(dev,
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STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
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STPMU1_BUCK_EN, STPMU1_BUCK_EN);
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if (ret < 0)
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return ret;
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mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
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ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
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STPMU1_VREF_EN, STPMU1_VREF_EN);
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if (ret < 0)
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return ret;
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mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
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/* Enable LDO3 */
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ret = pmic_clrsetbits(dev,
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STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
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STPMU1_LDO_EN, STPMU1_LDO_EN);
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if (ret < 0)
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return ret;
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mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
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return 0;
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}
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#endif
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