/*
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*********************************************************************************************************
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* AR100 SYSTEM
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* AR100 Software System Develop Kits
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* pmu module
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*
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* (c) Copyright 2012-2016, Sunny China
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* All Rights Reserved
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*
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* File : pmu.h
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* By : Sunny
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* Version : v1.0
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* Date : 2012-5-8
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* Descript: power management unit module public header.
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* Update : date auther ver notes
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* 2012-5-8 8:52:39 Sunny 1.0 Create this file.
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*********************************************************************************************************
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*/
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#ifndef __PMU_H__
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#define __PMU_H__
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#define NMI_INT_TYPE_PMU (0)
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#define NMI_INT_TYPE_RTC (1)
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#define NMI_INT_TYPE_PMU_OFFSET (0x1 << NMI_INT_TYPE_PMU)
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#define NMI_INT_TYPE_RTC_OFFSET (0x1 << NMI_INT_TYPE_RTC)
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#define PMU_STEP_DELAY_US (16)
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#define PMU_DCDC3_STEP_DELAY_US (40)
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#define AXP_TRANS_BYTE_MAX (8) /* the max number of pmu transfer byte */
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/*
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*********************************************************************************************************
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* PMU specific
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*********************************************************************************************************
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*/
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/* aw1736 voltage type */
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enum {
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AW1736_POWER_DCDC1 = 0x0,
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AW1736_POWER_DCDC2,
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AW1736_POWER_DCDC3,
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AW1736_POWER_DCDC4,
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AW1736_POWER_DCDC5,
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AW1736_POWER_DCDC6,
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AW1736_POWER_ALDO1,
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AW1736_POWER_ALDO2,
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AW1736_POWER_ALDO3,
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AW1736_POWER_ALDO4,
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AW1736_POWER_ALDO5,
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AW1736_POWER_BLDO1,
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AW1736_POWER_BLDO2,
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AW1736_POWER_BLDO3,
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AW1736_POWER_BLDO4,
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AW1736_POWER_BLDO5,
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AW1736_POWER_CLDO1,
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AW1736_POWER_CLDO2,
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AW1736_POWER_CLDO3,
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AW1736_POWER_CLDO4,
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AW1736_POWER_CPUSLDO,
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AW1736_POWER_LDOIO0,
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AW1736_POWER_LDOIO1,
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AW1736_POWER_DC1SW,
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AW1736_POWER_RTC,
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AW1736_POWER_MAX,
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};
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/* aw1669 voltage type */
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enum {
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AW1669_POWER_DCDC1 = 0x0,
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AW1669_POWER_DCDC2,
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AW1669_POWER_DCDC3,
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AW1669_POWER_DCDC4,
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AW1669_POWER_DCDC5,
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AW1669_POWER_RTC,
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AW1669_POWER_ALDO1,
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AW1669_POWER_ALDO2,
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AW1669_POWER_ALDO3,
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AW1669_POWER_DLDO1,
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AW1669_POWER_DLDO2,
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AW1669_POWER_ELDO1,
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AW1669_POWER_ELDO2,
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AW1669_POWER_ELDO3,
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AW1669_POWER_LDOIO0,
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AW1669_POWER_LDOIO1,
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AW1669_POWER_SWOUT,
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AW1669_POWER_DC1SW,
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AW1669_POWER_DC5LDO,
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AW1669_POWER_MAX,
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};
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/* aw2101 voltage type */
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enum {
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AXP2101_POWER_DCDC1 = 0x0,
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AXP2101_POWER_DCDC2,
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AXP2101_POWER_DCDC3,
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AXP2101_POWER_DCDC4,
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AXP2101_POWER_DCDC5,
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AXP2101_POWER_RTC1,
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AXP2101_POWER_ALDO1,
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AXP2101_POWER_ALDO2,
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AXP2101_POWER_ALDO3,
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AXP2101_POWER_ALDO4,
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AXP2101_POWER_BLDO1,
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AXP2101_POWER_BLDO2,
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AXP2101_POWER_CPUSLDO,
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AXP2101_POWER_DLDO1,
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AXP2101_POWER_DLDO2,
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AXP2101_POWER_MAX,
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};
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/*
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*********************************************************************************************************
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* PMU common
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*********************************************************************************************************
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*/
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typedef enum pmu_ioctl_type
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{
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IOCTL_PMU_READ = 0x1,
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IOCTL_PMU_WRITE,
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IOCTL_PMU_DISABLE_IRQ,
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IOCTL_PMU_ENABLE_IRQ,
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IOCTL_PMU_CLR_IRQ_STATUS,
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IOCTL_PMU_SET_IRQ_TRIGGER,
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IOCTL_PMU_SET_VOLT,
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IOCTL_PMU_GET_VOLT,
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IOCTL_PMU_SET_VOLT_STA,
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IOCTL_PMU_GET_VOLT_STA,
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IOCTL_PMU_RESET,
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IOCTL_PMU_SHUTDOWN,
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} pmu_ioctl_type_e;
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typedef enum power_key_type
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{
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POWER_KEY_SHORT = 1,
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POWER_KEY_LONG = 2,
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POWER_LOW_POWER = 3,
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} power_key_type_e;
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typedef enum power_voltage_state
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{
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POWER_VOL_OFF = 0x0,
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POWER_VOL_ON = 0x1,
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} power_voltage_state_e;
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typedef enum power_mode
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{
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POWER_MODE_AXP = 0,
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POWER_MODE_DUMMY = 1,
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POWER_MODE_PWM = 2,
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} power_mode_e;
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//keep the struct word align
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//by superm at 2014-2-13 15:34:09
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typedef struct pmu_onoff_reg_bitmap
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{
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u16 devaddr;
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u16 regaddr;
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u16 offset;
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u8 state;
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u8 dvm_st;
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} pmu_onoff_reg_bitmap_t;
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extern pmu_onoff_reg_bitmap_t pmu_onoff_reg_bitmap[];
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typedef struct pmu_paras
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{
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u8 *devaddr;
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u8 *regaddr;
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u8 *data;
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u32 len;
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} pmu_paras_t;
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#ifdef CFG_PMU_USED
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extern s32 pmu_init(void);
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extern s32 pmu_exit(void);
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#else
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#define pmu_init() (0)
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#define pmu_exit() (0)
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#endif
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#ifdef CFG_SUN8IW15P1
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extern s32 bmu_init(void);
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extern s32 bmu_exit(void);
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extern s32 pmu_set_boost(u32 state);
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#endif
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void pmu_shutdown(void);
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void pmu_reset(void);
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s32 pmu_set_voltage(u32 type, u32 voltage); //the voltage base on mV
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s32 pmu_get_voltage(u32 type);
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s32 pmu_set_voltage_state(u32 type, u32 state);
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//register read and write
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s32 pmu_reg_read(u8 *devaddr, u8 *regaddr, u8 *data, u32 len);
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s32 pmu_reg_write(u8 *devaddr, u8 *regaddr, u8 *data, u32 len);
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//s32 pmu_get_chip_id(struct message *pmessage);
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s32 pmu_get_chip_id(u32 *chip_id);
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//pmu standby process
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s32 pmu_standby_init(u32 event, u32 gpio_bitmap);
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s32 pmu_standby_exit(void);
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s32 pmu_query_event(u32 *event);
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int nmi_int_handler(void *parg, u32 intno);
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int get_nmi_int_type(void);
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u32 pmu_output_is_stable(u32 type);
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s32 pmu_get_voltage_state(u32 type);
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//s32 pmu_set_paras(struct message *pmessage);
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s32 pmu_set_paras(u32 *paras);
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//s32 set_pwr_tree(struct message *pmessage);
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s32 set_pwr_tree(u32 *paras);
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#ifdef CFG_PMU_CHRCUR_CRTL_USED
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void pmu_contrl_batchrcur(void);
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#endif
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s32 pmu_get_batconsum(void);
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u32 pmu_get_powerstate(u32 power_reg);
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extern s32 pmu_reg_write_para(pmu_paras_t *para);
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extern s32 pmu_reg_read_para(pmu_paras_t *para);
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extern void pmu_sysconfig_cfg(void);
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extern void pmu_set_lowpcons(void);
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extern void pmu_sys_lowpcons(void);
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extern s32 pmu_set_pok_time(int time);
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extern void pmu_poweroff_system(void);
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extern void pmu_reset_system(void);
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extern int pmu_set_gpio(unsigned int id, unsigned int state);
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extern s32 pmu_clear_pendings(void);
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extern bool pmu_pin_detect(void);
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extern u32 is_pmu_exist(void);
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extern void watchdog_reset(void);
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#endif //__PMU_H__
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