#ifndef __PIN_H__
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#define __PIN_H__
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#include "ibase.h"
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#include "driver.h"
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#define PIN_GRP_PL (0x1)
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#define PIN_GRP_PM (0x2)
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#define GPIO_GP_PL PIN_GRP_PL
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#define GPIO_GP_PM PIN_GRP_PM
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#define GPIO_PIN_0 0
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#define GPIO_PIN_1 1
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#define GPIO_PIN_2 2
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#define GPIO_PIN_3 3
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#define GPIO_PIN_4 4
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#define GPIO_PIN_5 5
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#define GPIO_PIN_6 6
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#define GPIO_PIN_7 7
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#define GPIO_PIN_8 8
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#define GPIO_PIN_9 9
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#define GPIO_PIN_10 10
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#define GPIO_PIN_11 11
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#define GPIO_PIN_12 12
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#define GPIO_PIN_13 13
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#define GPIO_PIN_14 14
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#define GPIO_PIN_15 15
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#define GPIO_PIN_16 16
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#define GPIO_PIN_17 17
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#define GPIO_PIN_18 18
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#define GPIO_PIN_19 19
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#define GPIO_PIN_20 20
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#define GPIO_PIN_21 21
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#define GPIO_PIN_22 22
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#define GPIO_PIN_23 23
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#define GPIO_PIN_24 24
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#define GPIO_PIN_25 25
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#define GPIO_PIN_26 26
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#define GPIO_PIN_27 27
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#define GPIO_PIN_28 28
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#define GPIO_PIN_29 29
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#define GPIO_PIN_30 30
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#define GPIO_PIN_31 31
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#define GPIO_FN_0 0
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#define GPIO_FN_1 1
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#define GPIO_FN_2 2
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#define GPIO_FN_3 3
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#define GPIO_FN_4 4
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#define GPIO_FN_5 5
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#define GPIO_FN_6 6
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#define GPIO_FN_7 7
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#define GPIO_EXTI_DISABLE 0
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#define GPIO_EXTI_ENABLE 1
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#define GPIO_CLK_HOSC 1
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#define GPIO_CLK_LOSC 0
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#define CPUS_GPIO_PL(num) (1 << num)
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#define CPUS_GPIO_PM(num) (1 << (num + 12))
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#define GPIO_EXTI_POSITIVE_EDGE 0x0
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#define GPIO_EXTI_NEGATIVE_EDGE 0x1
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#define GPIO_EXTI_HIGN_LEVEL 0x2
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#define GPIO_EXTI_LOW_LEVEL 0x3
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#define GPIO_EXTI_DOUBLE_EDGE 0x4
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typedef struct {
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u8 pin_grp;
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u8 pin_num;
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u8 pin_fn;
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u8 pin_driving;
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u8 pin_pull;
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u8 pin_exti_config;
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u8 pin_exti_ctrl;
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u8 pin_exti_pre;
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u8 pin_exti_clk;
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}pin_config;
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typedef struct {
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pin_config init_config;
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u8 pin_suspend;
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u8 pin_used;
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u8 pin_data;
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u8 pin_pending;
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__pISR_t exti_handler;
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void *owner;
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}pin_typedef;
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//------------------------------------------------------------------------------
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// pin pull status
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//------------------------------------------------------------------------------
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typedef enum pin_pull
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{
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GPIO_PULL_DISABLE = 0x00,
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GPIO_PULL_UP = 0x01,
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GPIO_PULL_DOWN = 0x02,
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GPIO_PULL_RESERVED = 0x03,
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GPIO_PULL_DEFAULT = 0xFF
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} pin_pull_e;
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//------------------------------------------------------------------------------
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// pin multi drive level
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//------------------------------------------------------------------------------
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typedef enum pin_multi_drive
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{
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GPIO_MULTI_DRIVE_0 = 0x00,
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GPIO_MULTI_DRIVE_1 = 0x01,
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}pin_multi_drive_e;
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s32 pin_set(pin_config *config,pin_typedef **owner);
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void pin_disable(pin_typedef *pin);
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void pin_exti_irq_request(pin_typedef *pin, __pISR_t handler);
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void pin_data_write(pin_typedef *pin,u32 data);
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u32 pin_data_read(pin_typedef *pin);
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u32 is_wanted_gpio_int(u32 pin_grp, u32 gpio_int_en);
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u32 is_cpux_gpio_pending(void);
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u32 pin_query_pending(pin_typedef *pin);
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u32 pin_clear_pending(pin_typedef *pin);
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s32 pin_enable_int(pin_typedef *pin);
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s32 pin_disable_int(pin_typedef *pin);
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s32 pl_irq_handler(void *p_arg,u32 intno);
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s32 pm_irq_handler(void *p_arg,u32 intno);
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s32 pin_wakeup_init(void *parg);
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s32 pin_wakeup_exit(void *parg);
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s32 default_pin_wakeup_init(void *parg);
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s32 default_pin_wakeup_exit(void *parg);
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s32 pinl_init(void);
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s32 pinm_init(void);
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s32 pin_suspend(arisc_device *dev);
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s32 pin_resume(arisc_device *dev);
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void pin_exit(void);
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typedef struct {
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arisc_device dev;
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arisc_driver *dri;
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}pin_device;
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#endif
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