; Copyright ARM Ltd 2005. All rights reserved.
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;==================================================================
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; This code provides basic global enable for a Cortex-A8 cache
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; and program flow prediction
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; This code must be run from a privileged mode
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;==================================================================
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AREA CORTEXA8CACHE, CODE, READONLY
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EXPORT core_init
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core_init
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;==================================================================
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; Global Enable for Cortex-A8 Instruction and Data Caching
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;==================================================================
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MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0
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ORR r0, r0, #(0x1 <<12) ; enable I Cache
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;BIC r0, r0, #(0x1 <<12) ; Clear bit 0
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ORR r0, r0, #(0x1 <<2) ; enable D Cache
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;BIC r0, r0, #(0x1 << 2) ; Clear bit 0
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ORR r0, r0, #0x1 ; enable MMU
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MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
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;==================================================================
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; Enable Cortex-A8 Level2 Unified Cache
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;==================================================================
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MRC p15, 0, r0, c1, c0, 1 ; Read Auxiliary Control Register
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ORR r0, r0, #2 ; L2EN bit, enable L2 cache
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;BIC r0, r0, #(0x1 << 1) ; L2EN bit, disable L2 cache
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;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
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ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
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ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache
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MCR p15, 0, r0, c1, c0, 1 ; Write Auxiliary Control Register
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;==================================================================
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; Cortex-A8 program flow prediction
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;==================================================================
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MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0
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ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction
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;BIC r0, r0, #(0x1 << 11) ; Disable all forms of branch prediction
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MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
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;==================================================================
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BX lr
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END ; mark the end of this file
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