#include <linux/bitops.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/mdio.h>
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#include <linux/timer.h>
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#include <linux/netdevice.h>
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#define MAXIO_PHY_VER "v1.8.1.4"
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#define MAXIO_PAGE_SELECT 0x1f
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#define MAXIO_MAE0621A_WORK_STATUS_REG 0x1d
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#define MAXIO_MAE0621A_CLK_MODE_REG 0x02
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#define MAXIO_PHYSR_P_A43 (0X1A)
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#define MAXIO_PHY_LINK (1<<2)
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#define MAXIO_PHY_DUPLEX (1<<3)
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#define MAXIO_PHY_SPEED (3<<4)
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#define MAXIO_PHY_1000M (0X20)
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#define MAXIO_PHY_100M (0X10)
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#define MAXIO_PHY_10M (0X00)
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#define AUTONEG_COMPLETED_INT_EN (0x8)
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#define LINKOK (0x4)
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#define AUTONEG_COMPLETED (0x8)
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#define PHY_READ(a,b) phy_read((a),(b))
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#define PHY_WRITE(a,b,c) phy_write((a),(b),(c))
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int maxio_read_paged(struct phy_device *phydev, int page, u32 regnum)
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{
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int ret = 0, oldpage;
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oldpage = PHY_READ(phydev, MAXIO_PAGE_SELECT);
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if (oldpage >= 0) {
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, page);
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ret = PHY_READ(phydev, regnum);
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}
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, oldpage);
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return ret;
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}
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int maxio_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val)
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{
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int ret = 0, oldpage;
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oldpage = PHY_READ(phydev, MAXIO_PAGE_SELECT);
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if (oldpage >= 0) {
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, page);
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ret = PHY_WRITE(phydev, regnum, val);
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}
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, oldpage);
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return ret;
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}
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int maxio_adcc_check(struct phy_device *phydev)
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{
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int ret = 0;
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int adcvalue;
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u32 regval;
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int i;
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maxio_write_paged(phydev, 0xd96, 0x2, 0x1fff );
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maxio_write_paged(phydev, 0xd96, 0x2, 0x1000 );
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for(i = 0; i < 4;i++)
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{
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regval = 0xf908 + i * 0x100;
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maxio_write_paged(phydev, 0xd8f, 0xb, regval );
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adcvalue = maxio_read_paged(phydev, 0xd92, 0xb);
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if(adcvalue & 0x1ff)
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{
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continue;
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}
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else
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{
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ret = -1;
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break;
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}
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}
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return ret;
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}
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int maxio_self_check(struct phy_device *phydev,int checknum)
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{
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int ret = 0;
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int i;
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for(i = 0;i < checknum; i++)
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{
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ret = maxio_adcc_check(phydev);
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if(0 == ret)
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{
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printk("MAE0621A READY\n");
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break;
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}
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else
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{
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maxio_write_paged(phydev, 0x0, 0x0, 0x1940 );
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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msleep(10);
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maxio_write_paged(phydev, 0x0, 0x0, 0x1140 );
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maxio_write_paged(phydev, 0x0, 0x0, 0x9140 );
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}
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}
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maxio_write_paged(phydev, 0xd96, 0x2, 0xfff );
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maxio_write_paged(phydev, 0x0, 0x0, 0x9140 );
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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return ret;
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}
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static int maxio_mae0621a_resume(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_resume(phydev);
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ret |= PHY_WRITE(phydev, MII_BMCR, BMCR_RESET | PHY_READ(phydev, MII_BMCR));
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msleep(20);
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return ret;
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}
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static int maxio_mae0621a_suspend(struct phy_device *phydev)
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{
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int ret = 0;
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ret = genphy_suspend(phydev);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT ,0);
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return ret;
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}
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int maxio_restart_aneg(struct phy_device *phydev)
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{
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int ctl = PHY_READ(phydev, MII_BMCR);
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if (ctl < 0)
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return ctl;
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ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
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ctl &= ~BMCR_ISOLATE;
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return PHY_WRITE(phydev, MII_BMCR, ctl);
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}
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static void phy_resolve_aneg_linkmode_maxio(struct phy_device *phydev){
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int physr_p_a43 = maxio_read_paged(phydev,0xa43,MAXIO_PHYSR_P_A43);
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if((physr_p_a43&MAXIO_PHY_SPEED)==MAXIO_PHY_1000M){
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phydev->speed=SPEED_1000;
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}else if((physr_p_a43&MAXIO_PHY_SPEED)==MAXIO_PHY_100M){
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phydev->speed=SPEED_100;
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}else if((physr_p_a43&MAXIO_PHY_SPEED)==MAXIO_PHY_10M){
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phydev->speed=SPEED_10;
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}
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if(physr_p_a43 & MAXIO_PHY_DUPLEX){
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phydev->duplex=DUPLEX_FULL;
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}else{
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phydev->duplex=DUPLEX_HALF;
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}
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if(phydev->duplex==DUPLEX_FULL){
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int lpa=PHY_READ(phydev,MII_LPA);
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phydev->pause=(lpa&LPA_PAUSE_CAP)?1:0;
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phydev->asym_pause=(lpa&LPA_PAUSE_ASYM)?1:0;
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}
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}
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void phy_resolve_link_compatibility_maxio(struct phy_device *phydev)
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{
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int *paras = (int *)phydev->priv;
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int maxio_an_times = paras[0];
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int link_stable = paras[1];
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int iner, physr, insr;
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iner = maxio_read_paged(phydev, 0xa42, 0x12);
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if(iner&AUTONEG_COMPLETED_INT_EN){
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physr = maxio_read_paged(phydev, 0xa43, 0x1a);
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if(physr & LINKOK)
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{
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insr = maxio_read_paged(phydev, 0xa43, 0x1d);
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if((insr & AUTONEG_COMPLETED) == 0 && (link_stable == 0)){
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if(maxio_an_times < 4 ){
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maxio_restart_aneg(phydev);
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phydev->link = 0;
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maxio_an_times++;
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}
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else if(maxio_an_times == 4){
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link_stable = 1;
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}
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}
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else if(insr & AUTONEG_COMPLETED){
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maxio_an_times = 0;
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link_stable = 1;
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}
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if (link_stable == 1)
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maxio_an_times = 0;
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}
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else
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link_stable = 0;
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}
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paras[0] = maxio_an_times;
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paras[1] = link_stable;
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}
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static int maxio_mae0621a_status(struct phy_device *phydev)
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{
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int err, old_link = phydev->link;
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err = genphy_update_link(phydev);
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if (err)
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return err;
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if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
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return 0;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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phy_resolve_aneg_linkmode_maxio(phydev);
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if(phydev->autoneg == AUTONEG_ENABLE)
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phy_resolve_link_compatibility_maxio(phydev);
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return 0;
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}
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static void maxio_mae0621a_remove(struct phy_device *phydev)
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{
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printk("maxio driver remove\r\n");
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if(phydev->priv!=NULL){
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kfree(phydev->priv);
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}
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phydev->priv=NULL;
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}
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static int maxio_mae0621a_clk_init(struct phy_device *phydev)
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{
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u32 workmode,clkmode,oldpage;
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oldpage = PHY_READ(phydev, MAXIO_PAGE_SELECT);
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if (oldpage == 0xFFFF) {
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oldpage = PHY_READ(phydev, MAXIO_PAGE_SELECT);
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}
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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PHY_WRITE(phydev, MII_BMCR, 0x9140);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0xa43);
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workmode = PHY_READ(phydev, MAXIO_MAE0621A_WORK_STATUS_REG);
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PHY_WRITE( phydev, MAXIO_PAGE_SELECT, 0xd92 );
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clkmode = PHY_READ( phydev, MAXIO_MAE0621A_CLK_MODE_REG );
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if (0 == (workmode&BIT(5))) {
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if (0 == (clkmode&BIT(8))) {
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PHY_WRITE(phydev, 0x02, clkmode | BIT(8));
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printk("****maxio_mae0621a_clk_init**clkmode**0x210a: 0x%x\n", phydev->phy_id);
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} else {
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printk("****maxio_mae0621a_clk_init**clkmode**0x200a: 0x%x\n", phydev->phy_id);
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PHY_WRITE(phydev, 0x02, clkmode &(~ BIT(8)));
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}
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}
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, oldpage);
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msleep(1000);
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return 0;
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}
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static int maxio_mae0621a_config_init(struct phy_device *phydev)
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{
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int ret = 0;
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printk("MAXIO_PHY_VER: %s \n",MAXIO_PHY_VER);
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maxio_mae0621a_clk_init(phydev);
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ret |= maxio_write_paged(phydev, 0xda0, 0x10, 0xc13);
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ret |= maxio_write_paged(phydev, 0x0, 0xd, 0x7);
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ret |= maxio_write_paged(phydev, 0x0, 0xe, 0x3c);
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ret |= maxio_write_paged(phydev, 0x0, 0xd, 0x4007);
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ret |= maxio_write_paged(phydev, 0x0, 0xe, 0x0);
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ret |= maxio_write_paged(phydev, 0xd96, 0x13, 0x7bc);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x8, 0x2500);
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ret |= maxio_write_paged(phydev, 0xd90, 0x2, 0x1555);
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ret |= maxio_write_paged(phydev, 0xd90, 0x5, 0x2b15);
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ret |= maxio_write_paged(phydev, 0xd92, 0x14, 0xa);
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ret |= maxio_write_paged(phydev, 0xd91, 0x7, 0x5b00);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x0, 0x300);
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ret |= maxio_write_paged(phydev, 0xd92, 0xa, 0x8506);
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ret |= maxio_write_paged(phydev, 0xd91, 0x6, 0x6870);
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ret |= maxio_write_paged(phydev, 0xd91, 0x1, 0x940);
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ret |= maxio_write_paged(phydev, 0xda0, 0x13, 0x1303);
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ret |= maxio_write_paged(phydev, 0xd97, 0xc, 0x177);
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ret |= maxio_write_paged(phydev, 0xd97, 0xb, 0x9a9);
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ret |= maxio_write_paged(phydev, 0xa42, 0x12, 0x28);
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ret |= maxio_write_paged(phydev, 0x0, 0x4, 0xde1);
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ret |= maxio_write_paged(phydev, 0x0, 0x0, 0x9140);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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ret |= maxio_self_check(phydev,50);
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msleep(100);
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return 0;
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}
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static int maxio_mae0621a_probe(struct phy_device *phydev)
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{
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int *paras;
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paras = kzalloc( 2 * sizeof(int), GFP_KERNEL);
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if(!paras)
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return -ENOMEM;
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phydev->priv = paras;
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maxio_mae0621a_clk_init(phydev);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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mdelay(100);
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return 0;
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}
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static int maxio_mae0621aq3ci_probe(struct phy_device *phydev)
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{
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int *paras;
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paras = kzalloc( 2 * sizeof(int), GFP_KERNEL);
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if(!paras)
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return -ENOMEM;
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phydev->priv = paras;
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printk("maxio_mae0621aQ3C probe PHY_ID: 0x%x\n", phydev->phy_id);
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return 0;
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}
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static int maxio_mae0621aq3ci_config_init(struct phy_device *phydev)
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{
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int ret = 0;
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printk("MAXIO_PHY_VER: %s \n",MAXIO_PHY_VER);
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ret |= maxio_write_paged(phydev, 0xa43, 0x19, 0x823);
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ret |= maxio_write_paged(phydev, 0xdab, 0x17, 0xC13);
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ret |= maxio_write_paged(phydev, 0xd96, 0x15, 0xc08a);
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ret |= maxio_write_paged(phydev, 0xda4, 0x12, 0x7bc);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x16, 0x2500);
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ret |= maxio_write_paged(phydev, 0xd90, 0x16, 0x1555);
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ret |= maxio_write_paged(phydev, 0xd92, 0x11, 0x2b15);
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ret |= maxio_write_paged(phydev, 0xd96, 0x16, 0x4010);
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ret |= maxio_write_paged(phydev, 0xda5, 0x11, 0x4a12);
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ret |= maxio_write_paged(phydev, 0xda5, 0x12, 0x4a12);
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ret |= maxio_write_paged(phydev, 0xd99, 0x16, 0xa);
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ret |= maxio_write_paged(phydev, 0xd95, 0x13, 0x5b00);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x10, 0x300);
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ret |= maxio_write_paged(phydev, 0xd98, 0x17, 0x8506);
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ret |= maxio_write_paged(phydev, 0xd95, 0x12, 0x6870);
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ret |= maxio_write_paged(phydev, 0xd93, 0x15, 0x940);
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ret |= maxio_write_paged(phydev, 0xdad, 0x12, 0x1303);
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ret |= maxio_write_paged(phydev, 0xda8, 0x11, 0x177);
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ret |= maxio_write_paged(phydev, 0xda8, 0x10, 0x9a9);
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ret |= maxio_write_paged(phydev, 0xa42, 0x12, 0x28);
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ret |= maxio_write_paged(phydev, 0x0, 0x4, 0xde1);
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ret |= maxio_write_paged(phydev, 0x0, 0x0, 0x9140);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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return 0;
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}
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static int maxio_mae0621aq3ci_resume(struct phy_device *phydev)
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{
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int ret = 0;
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ret = genphy_resume(phydev);
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ret |= maxio_write_paged(phydev, 0xdaa, 0x17, 0x1001 );
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ret |= maxio_write_paged(phydev, 0xdab, 0x15, 0x0 );
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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return ret;
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}
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static int maxio_mae0621aq3ci_suspend(struct phy_device *phydev)
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{
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int ret = 0;
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ret = maxio_write_paged(phydev, 0xdaa, 0x17, 0x1011 );
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ret |= maxio_write_paged(phydev, 0xdab, 0x15, 0x5550 );
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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ret |= genphy_suspend(phydev);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT ,0);
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return ret;
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}
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static struct phy_driver maxio_nc_drvs[] = {
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{
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.phy_id = 0x7b744411,
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.phy_id_mask = 0x7fffffff,
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.name = "MAE0621A-Q2C Gigabit Ethernet",
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.features = PHY_GBIT_FEATURES ,
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.probe = maxio_mae0621a_probe,
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.config_init = maxio_mae0621a_config_init,
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.config_aneg = &genphy_config_aneg,
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.read_status = maxio_mae0621a_status,
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.suspend = maxio_mae0621a_suspend,
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.resume = maxio_mae0621a_resume,
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.remove = maxio_mae0621a_remove,
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},
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{
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.phy_id = 0x7b744412,
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.phy_id_mask = 0x7fffffff,
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.name = "MAE0621A/B-Q3C(I) Gigabit Ethernet",
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.features = PHY_GBIT_FEATURES ,
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.probe = maxio_mae0621aq3ci_probe,
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.config_aneg = &genphy_config_aneg,
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.config_init = maxio_mae0621aq3ci_config_init,
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.read_status = &maxio_mae0621a_status,
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.suspend = maxio_mae0621aq3ci_suspend,
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.resume = maxio_mae0621aq3ci_resume,
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.remove = maxio_mae0621a_remove,
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},
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};
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module_phy_driver(maxio_nc_drvs);
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static struct mdio_device_id __maybe_unused maxio_nc_tbl[] = {
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{ 0x7b744411, 0x7fffffff },
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{ 0x7b744412, 0x7fffffff },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, maxio_nc_tbl);
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MODULE_DESCRIPTION("Maxio PHY driver");
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MODULE_AUTHOR("Zhao Yang");
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MODULE_LICENSE("GPL");
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