/*
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* Copyright (C) 2018 Allwinner Technology Limited. All rights reserved.
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* Albert Yu <yuxyun@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __LINUX_LEDS_SUNXI_H
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#define __LINUX_LEDS_SUNXI_H
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/rwsem.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <linux/workqueue.h>
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#define HEXADECIMAL (0x10)
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#define REG_INTERVAL (0x04)
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#define REG_CL (0x0c)
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#define RESULT_COMPLETE 1
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#define RESULT_ERR 2
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#define SUNXI_LEDC_REG_BASE_ADDR 0x06700000
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#define SUNXI_MAX_LED_COUNT 1024
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#define SUNXI_DEFAULT_LED_COUNT 8
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#define SUNXI_RESET_TIME_MIN_NS 84
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#define SUNXI_RESET_TIME_MAX_NS 327000
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#define SUNXI_T1H_MIN_NS 84
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#define SUNXI_T1H_MAX_NS 2560
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#define SUNXI_T1L_MIN_NS 84
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#define SUNXI_T1L_MAX_NS 1280
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#define SUNXI_T0H_MIN_NS 84
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#define SUNXI_T0H_MAX_NS 1280
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#define SUNXI_T0L_MIN_NS 84
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#define SUNXI_T0L_MAX_NS 2560
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#define SUNXI_WAIT_TIME0_MIN_NS 84
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#define SUNXI_WAIT_TIME0_MAX_NS 10000
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#define SUNXI_WAIT_TIME1_MIN_NS 84
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#define SUNXI_WAIT_TIME1_MAX_NS 85000000000
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#define SUNXI_WAIT_DATA_TIME_MIN_NS 84
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#define SUNXI_WAIT_DATA_TIME_MAX_NS_IC 655000
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#define SUNXI_WAIT_DATA_TIME_MAX_NS_FPGA 20000000
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#define SUNXI_LEDC_FIFO_DEPTH 32 /* 32 * 4 bytes */
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#define SUNXI_LEDC_FIFO_TRIG_LEVEL 15
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#if defined(CONFIG_FPGA_V4_PLATFORM) || defined(CONFIG_FPGA_V7_PLATFORM)
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#define SUNXI_FPGA_LEDC
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#endif
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enum sunxi_ledc_output_mode_val {
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SUNXI_OUTPUT_GRB = 0 << 6,
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SUNXI_OUTPUT_GBR = 1 << 6,
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SUNXI_OUTPUT_RGB = 2 << 6,
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SUNXI_OUTPUT_RBG = 3 << 6,
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SUNXI_OUTPUT_BGR = 4 << 6,
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SUNXI_OUTPUT_BRG = 5 << 6
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};
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struct sunxi_ledc_output_mode {
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char *str;
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enum sunxi_ledc_output_mode_val val;
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};
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enum sunxi_ledc_trans_mode_val {
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LEDC_TRANS_CPU_MODE,
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LEDC_TRANS_DMA_MODE
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};
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enum sunxi_ledc_reg {
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LEDC_CTRL_REG_OFFSET = 0x00,
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LED_T01_TIMING_CTRL_REG_OFFSET = 0x04,
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LEDC_DATA_FINISH_CNT_REG_OFFSET = 0x08,
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LED_RESET_TIMING_CTRL_REG_OFFSET = 0x0c,
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LEDC_WAIT_TIME0_CTRL_REG = 0x10,
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LEDC_DATA_REG_OFFSET = 0x14,
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LEDC_DMA_CTRL_REG = 0x18,
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LEDC_INT_CTRL_REG_OFFSET = 0x1c,
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LEDC_INT_STS_REG_OFFSET = 0x20,
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LEDC_WAIT_TIME1_CTRL_REG = 0x28,
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LEDC_VER_NUM_REG = 0x2c,
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LEDC_FIFO_DATA = 0x30,
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LEDC_TOTAL_REG_SIZE = LEDC_FIFO_DATA + SUNXI_LEDC_FIFO_DEPTH
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};
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enum sunxi_ledc_irq_ctrl_reg {
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LEDC_TRANS_FINISH_INT_EN = (1 << 0),
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LEDC_FIFO_CPUREQ_INT_EN = (1 << 1),
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LEDC_WAITDATA_TIMEOUT_INT_EN = (1 << 3),
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LEDC_FIFO_OVERFLOW_INT_EN = (1 << 4),
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LEDC_GLOBAL_INT_EN = (1 << 5),
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};
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enum sunxi_ledc_irq_status_reg {
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LEDC_TRANS_FINISH_INT = (1 << 0),
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LEDC_FIFO_CPUREQ_INT = (1 << 1),
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LEDC_WAITDATA_TIMEOUT_INT = (1 << 3),
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LEDC_FIFO_OVERFLOW_INT = (1 << 4),
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LEDC_FIFO_FULL = (1 << 16),
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LEDC_FIFO_EMPTY = (1 << 17),
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};
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enum sunxi_led_type {
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LED_TYPE_R,
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LED_TYPE_G,
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LED_TYPE_B
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};
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struct sunxi_led_info {
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enum sunxi_led_type type;
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struct led_classdev cdev;
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};
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struct sunxi_led_classdev_group {
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u32 led_num;
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struct sunxi_led_info r;
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struct sunxi_led_info g;
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struct sunxi_led_info b;
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};
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struct sunxi_led {
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u32 reset_ns;
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u32 t1h_ns;
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u32 t1l_ns;
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u32 t0h_ns;
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u32 t0l_ns;
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u32 wait_time0_ns;
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unsigned long long wait_time1_ns;
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u32 wait_data_time_ns;
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u32 irqnum;
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u32 led_count;
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u32 *data;
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u32 length;
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u8 result;
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spinlock_t lock;
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struct device *dev;
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dma_addr_t src_dma;
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struct dma_chan *dma_chan;
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wait_queue_head_t wait;
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struct timespec64 start_time;
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struct clk *clk_ledc;
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struct clk *clk_cpuapb;
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struct pinctrl *pctrl;
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void __iomem *iomem_reg_base;
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struct resource *res;
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struct sunxi_ledc_output_mode output_mode;
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struct sunxi_led_classdev_group *pcdev_group;
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struct dentry *debugfs_dir;
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char regulator_id[16];
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struct regulator *regulator;
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};
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enum {
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DEBUG_INIT = 1U << 0,
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DEBUG_SUSPEND = 1U << 1,
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DEBUG_INFO = 1U << 2,
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DEBUG_INFO1 = 1U << 3,
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DEBUG_INFO2 = 1U << 4,
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};
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#endif /* __LINUX_LEDS_SUNXI_H */
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