/* g2d_regs.h
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*
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* Copyright (c) 2011 Allwinnertech Co., Ltd.
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* 2011 Yupu Tang
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*
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* G2D driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef __G2D_MIXER_REGS_H
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#define __G2D_MIXER_REGS_H
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/*
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*Graphics 2D General Registers
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*/
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#define G2D_BASE_ADDR (0x01e80000)/* Base Address */
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#define G2D_CONTROL_REG (0x00) /* Control register */
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#define G2D_STATUS_REG (0x04) /* Status register */
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/* DMA scan order control register */
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#define G2D_SCAN_ORDER_REG (0x08)
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/*
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* Graphics 2D Input Address Parameter Setting Registers
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*/
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/* Input DMA high 4 bits start addr register */
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#define G2D_DMA_HADDR_REG (0x0c)
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/* Input DMA0 low 32 bits start addr register */
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#define G2D_DMA0_LADDR_REG (0x10)
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/* Input DMA1 low 32 bits start addr register */
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#define G2D_DMA1_LADDR_REG (0x14)
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/* Input DMA2 low 32 bits start addr register */
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#define G2D_DMA2_LADDR_REG (0x18)
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/* Input DMA3 low 32 bits start addr register */
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#define G2D_DMA3_LADDR_REG (0x1c)
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/*
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* Graphics 2D Input Linewidth Buffer Parameter Setting Registers
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*/
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/* Input DMA0 line stride register */
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#define G2D_DMA0_STRIDE_REG (0x20)
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/* Input DMA1 line stride register */
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#define G2D_DMA1_STRIDE_REG (0x24)
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/* Input DMA2 line stride register */
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#define G2D_DMA2_STRIDE_REG (0x28)
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/* Input DMA3 line stride register */
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#define G2D_DMA3_STRIDE_REG (0x2c)
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/* Input DMA0 memory block size register */
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#define G2D_DMA0_SIZE_REG (0x30)
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/* Input DMA1 memory block size register */
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#define G2D_DMA1_SIZE_REG (0x34)
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/* Input DMA2 memory block size register */
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#define G2D_DMA2_SIZE_REG (0x38)
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/* Input DMA3 memory block size register */
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#define G2D_DMA3_SIZE_REG (0x3c)
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/* Input DMA0 memory block coordinate register */
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#define G2D_DMA0_COOR_REG (0x40)
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/* Input DMA1 memory block coordinate register */
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#define G2D_DMA1_COOR_REG (0x44)
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/* Input DMA2 memory block coordinate register */
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#define G2D_DMA2_COOR_REG (0x48)
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/* Input DMA3 memory block coordinate register */
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#define G2D_DMA3_COOR_REG (0x4c)
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/* Input DMA0 control register */
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#define G2D_DMA0_CONTROL_REG (0x50)
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/* Input DMA1 control register */
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#define G2D_DMA1_CONTROL_REG (0x54)
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/* Input DMA2 control register */
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#define G2D_DMA2_CONTROL_REG (0x58)
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/* Input DMA3 control register */
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#define G2D_DMA3_CONTROL_REG (0x5c)
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/* Input DMA0 fillcolor register */
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#define G2D_DMA0_FILLCOLOR_REG (0x60)
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/* Input DMA1 fillcolor register */
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#define G2D_DMA1_FILLCOLOR_REG (0x64)
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/* Input DMA2 fillcolor register */
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#define G2D_DMA2_FILLCOLOR_REG (0x68)
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/* Input DMA3 fillcolor register */
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#define G2D_DMA3_FILLCOLOR_REG (0x6c)
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/* Color space converter0 control register */
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#define G2D_CSC0_CONTROL_REG (0x74)
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/* Color space converter1 control register */
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#define G2D_CSC1_CONTROL_REG (0x78)
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/* Scaler control register */
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#define G2D_SCALER_CONTROL_REG (0x80)
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/* Scaler output size control register */
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#define G2D_SCALER_SIZE_REG (0x84)
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/* Scaler horizontal scaling factor register */
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#define G2D_SCALER_HFACTOR_REG (0x88)
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/* Scaler vertical scaling factor register */
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#define G2D_SCALER_VFACTOR_REG (0x8c)
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/* Scaler horizontal start phase register */
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#define G2D_SCALER_HPHASE_REG (0x90)
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/* Scaler vertical start phase register */
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#define G2D_SCALER_VPHASE_REG (0x94)
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/* Rop control register */
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#define G2D_ROP_CONTROL_REG (0xb0)
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/* Rop index0 control table setting register */
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#define G2D_ROP_INDEX0_REG (0xb8)
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/* Rop index1 control table setting register */
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#define G2D_ROP_INDEX1_REG (0xbc)
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/* Colorkey/alpha control register */
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#define G2D_CK_CONTROL_REG (0xc0)
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/* Colorkey min color control register */
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#define G2D_CK_MINCOLOR_REG (0xc4)
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/* Colorkey max color control register */
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#define G2D_CK_MAXCOLOR_REG (0xc8)
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/* Rop output fillcolor setting register */
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#define G2D_ROP_FILLCOLOR_REG (0xcc)
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/* Color space converter2 control register */
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#define G2D_CSC2_CONTROL_REG (0xd0)
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/* Output control register */
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#define G2D_OUTPUT_CONTROL_REG (0xe0)
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/* Output size register */
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#define G2D_OUTPUT_SIZE_REG (0xe8)
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/* Output high 4 bits address control register */
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#define G2D_OUTPUT_HADDR_REG (0xec)
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/* Output low 32 bits address control register */
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#define G2D_OUTPUT0_LADDR_REG (0xf0)
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/* Output low 32 bits address control register */
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#define G2D_OUTPUT1_LADDR_REG (0xf4)
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/* Output low 32 bits address control register */
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#define G2D_OUTPUT2_LADDR_REG (0xf8)
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/* Output channel0 line stride control register */
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#define G2D_OUTPUT0_STRIDE_REG (0x100)
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/* Output channel1 line stride control register */
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#define G2D_OUTPUT1_STRIDE_REG (0x104)
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/* Output channel2 line stride control register */
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#define G2D_OUTPUT2_STRIDE_REG (0x108)
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/* Output alpha control register */
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#define G2D_OALPHA_CONTROL_REG (0x120)
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/* Input DMA0 micro block control register */
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#define G2D_DMA0_MBCTL_REG (0x130)
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/* Input DMA1 micro block control register */
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#define G2D_DMA1_MBCTL_REG (0x134)
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/* Input DMA2 micro block control register */
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#define G2D_DMA2_MBCTL_REG (0x138)
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/* Input DMA3 micro block control register */
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#define G2D_DMA3_MBCTL_REG (0x13c)
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/* command queue control register */
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#define G2D_CMDQ_CTL_REG (0x140)
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/* command queue status register */
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#define G2D_CMDQ_STS_REG (0x144)
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/* command queue storage start address register */
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#define G2D_CMDQ_ADDR_REG (0x148)
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/* CSC0/1 coefficient/constant start addr register(0x180-0x1ac) */
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#define G2D_CSC01_ADDR_REG (0x180)
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/* CSC2 coefficient/constant start addr register(0x1c0-0x1ec) */
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#define G2D_CSC2_ADDR_REG (0x1c0)
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/* Scaling horizontal filtering coefficient ram block register(0x200-0x27c) */
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#define G2D_SCALER_HFILTER_REG (0x200)
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/* Scaling vertical filtering coefficient ram block register(0x280-0x2fc) */
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#define G2D_SCALER_VFILTER_REG (0x280)
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/* Scaling horizontal filtering coefficient ram block register(0x400-0x7fc) */
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#define G2D_PALETTE_TAB_REG (0x400)
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/* Input DMA setting */
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#define G2D_FILL_ENABLE (1<<16)
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#define G2D_FILL_DISABLE (0<<16)
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/* Work Mode Select */
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#define G2D_IDMA_ENABLE (1<<0)
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#define G2D_IDMA_DISABLE (0<<0)
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/* Scaler Control Select */
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#define G2D_SCALER_DISABLE (0<<0)
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#define G2D_SCALER_ENABLE (1<<0)
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#define G2D_SCALER_4TAP4 (0<<4)
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/* byte input */
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#define get_bvalue(n) (*((volatile __u8 *)(n)))
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/* byte output */
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#define put_bvalue(n, c) (*((volatile __u8 *)(n)) = (c))
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/* half word input */
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#define get_hvalue(n) (*((volatile __u16 *)(n)))
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/* half word output */
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#define put_hvalue(n, c) (*((volatile __u16 *)(n)) = (c))
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/* word input */
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#define get_wvalue(n) (*((volatile __u32 *)(n)))
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/* word output */
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#define put_wvalue(n, c) (*((volatile __u32 *)(n)) = (c))
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#endif /* __G2D_MIXER_REGS_H */
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