// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_REGISTER_CONFIGURATION_H_
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#define V8_REGISTER_CONFIGURATION_H_
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#include "src/base/macros.h"
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#include "src/globals.h"
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#include "src/machine-type.h"
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#include "src/reglist.h"
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namespace v8 {
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namespace internal {
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// An architecture independent representation of the sets of registers available
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// for instruction creation.
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class V8_EXPORT_PRIVATE RegisterConfiguration {
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public:
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enum AliasingKind {
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// Registers alias a single register of every other size (e.g. Intel).
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OVERLAP,
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// Registers alias two registers of the next smaller size (e.g. ARM).
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COMBINE
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};
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// Architecture independent maxes.
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static const int kMaxGeneralRegisters = 32;
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static const int kMaxFPRegisters = 32;
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// Default RegisterConfigurations for the target architecture.
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static const RegisterConfiguration* Default();
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// Register configuration with reserved masking register.
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static const RegisterConfiguration* Poisoning();
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// Register configuration with reserved root register on ia32.
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static const RegisterConfiguration* PreserveRootIA32();
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static const RegisterConfiguration* RestrictGeneralRegisters(
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RegList registers);
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RegisterConfiguration(int num_general_registers, int num_double_registers,
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int num_allocatable_general_registers,
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int num_allocatable_double_registers,
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const int* allocatable_general_codes,
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const int* allocatable_double_codes,
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AliasingKind fp_aliasing_kind,
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char const* const* general_names,
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char const* const* float_names,
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char const* const* double_names,
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char const* const* simd128_names);
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int num_general_registers() const { return num_general_registers_; }
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int num_float_registers() const { return num_float_registers_; }
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int num_double_registers() const { return num_double_registers_; }
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int num_simd128_registers() const { return num_simd128_registers_; }
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int num_allocatable_general_registers() const {
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return num_allocatable_general_registers_;
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}
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int num_allocatable_float_registers() const {
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return num_allocatable_float_registers_;
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}
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int num_allocatable_double_registers() const {
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return num_allocatable_double_registers_;
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}
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int num_allocatable_simd128_registers() const {
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return num_allocatable_simd128_registers_;
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}
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AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; }
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int32_t allocatable_general_codes_mask() const {
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return allocatable_general_codes_mask_;
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}
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int32_t allocatable_double_codes_mask() const {
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return allocatable_double_codes_mask_;
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}
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int32_t allocatable_float_codes_mask() const {
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return allocatable_float_codes_mask_;
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}
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int GetAllocatableGeneralCode(int index) const {
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DCHECK(index >= 0 && index < num_allocatable_general_registers());
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return allocatable_general_codes_[index];
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}
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bool IsAllocatableGeneralCode(int index) const {
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return ((1 << index) & allocatable_general_codes_mask_) != 0;
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}
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int GetAllocatableFloatCode(int index) const {
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DCHECK(index >= 0 && index < num_allocatable_float_registers());
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return allocatable_float_codes_[index];
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}
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bool IsAllocatableFloatCode(int index) const {
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return ((1 << index) & allocatable_float_codes_mask_) != 0;
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}
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int GetAllocatableDoubleCode(int index) const {
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DCHECK(index >= 0 && index < num_allocatable_double_registers());
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return allocatable_double_codes_[index];
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}
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bool IsAllocatableDoubleCode(int index) const {
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return ((1 << index) & allocatable_double_codes_mask_) != 0;
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}
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int GetAllocatableSimd128Code(int index) const {
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DCHECK(index >= 0 && index < num_allocatable_simd128_registers());
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return allocatable_simd128_codes_[index];
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}
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bool IsAllocatableSimd128Code(int index) const {
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return ((1 << index) & allocatable_simd128_codes_mask_) != 0;
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}
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const char* GetGeneralOrSpecialRegisterName(int code) const;
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const char* GetGeneralRegisterName(int code) const {
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DCHECK_LT(code, num_general_registers_);
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return general_register_names_[code];
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}
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const char* GetFloatRegisterName(int code) const {
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return float_register_names_[code];
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}
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const char* GetDoubleRegisterName(int code) const {
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return double_register_names_[code];
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}
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const char* GetSimd128RegisterName(int code) const {
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return simd128_register_names_[code];
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}
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const int* allocatable_general_codes() const {
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return allocatable_general_codes_;
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}
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const int* allocatable_float_codes() const {
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return allocatable_float_codes_;
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}
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const int* allocatable_double_codes() const {
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return allocatable_double_codes_;
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}
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const int* allocatable_simd128_codes() const {
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return allocatable_simd128_codes_;
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}
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// Aliasing calculations for floating point registers, when fp_aliasing_kind()
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// is COMBINE. Currently only implemented for kFloat32, kFloat64, or kSimd128
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// reps. Returns the number of aliases, and if > 0, alias_base_index is set to
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// the index of the first alias.
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int GetAliases(MachineRepresentation rep, int index,
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MachineRepresentation other_rep, int* alias_base_index) const;
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// Returns a value indicating whether two registers alias each other, when
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// fp_aliasing_kind() is COMBINE. Currently implemented for kFloat32,
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// kFloat64, or kSimd128 reps.
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bool AreAliases(MachineRepresentation rep, int index,
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MachineRepresentation other_rep, int other_index) const;
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virtual ~RegisterConfiguration() {}
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private:
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const int num_general_registers_;
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int num_float_registers_;
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const int num_double_registers_;
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int num_simd128_registers_;
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int num_allocatable_general_registers_;
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int num_allocatable_float_registers_;
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int num_allocatable_double_registers_;
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int num_allocatable_simd128_registers_;
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int32_t allocatable_general_codes_mask_;
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int32_t allocatable_float_codes_mask_;
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int32_t allocatable_double_codes_mask_;
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int32_t allocatable_simd128_codes_mask_;
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const int* allocatable_general_codes_;
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int allocatable_float_codes_[kMaxFPRegisters];
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const int* allocatable_double_codes_;
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int allocatable_simd128_codes_[kMaxFPRegisters];
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AliasingKind fp_aliasing_kind_;
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char const* const* general_register_names_;
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char const* const* float_register_names_;
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char const* const* double_register_names_;
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char const* const* simd128_register_names_;
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};
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} // namespace internal
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} // namespace v8
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#endif // V8_REGISTER_CONFIGURATION_H_
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