// Copyright 2011 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// Declares a Simulator for MIPS instructions if we are not generating a native
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// MIPS binary. This Simulator allows us to run and debug MIPS code generation
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// on regular desktop machines.
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// V8 calls into generated code via the GeneratedCode wrapper,
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// which will start execution in the Simulator or forwards to the real entry
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// on a MIPS HW platform.
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#ifndef V8_MIPS64_SIMULATOR_MIPS64_H_
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#define V8_MIPS64_SIMULATOR_MIPS64_H_
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#include "src/allocation.h"
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#include "src/mips64/constants-mips64.h"
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#if defined(USE_SIMULATOR)
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// Running with a simulator.
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#include "src/assembler.h"
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#include "src/base/hashmap.h"
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#include "src/simulator-base.h"
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namespace v8 {
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namespace internal {
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// -----------------------------------------------------------------------------
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// Utility functions
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class CachePage {
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public:
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static const int LINE_VALID = 0;
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static const int LINE_INVALID = 1;
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static const int kPageShift = 12;
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static const int kPageSize = 1 << kPageShift;
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static const int kPageMask = kPageSize - 1;
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static const int kLineShift = 2; // The cache line is only 4 bytes right now.
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static const int kLineLength = 1 << kLineShift;
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static const int kLineMask = kLineLength - 1;
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CachePage() {
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memset(&validity_map_, LINE_INVALID, sizeof(validity_map_));
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}
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char* ValidityByte(int offset) {
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return &validity_map_[offset >> kLineShift];
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}
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char* CachedData(int offset) {
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return &data_[offset];
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}
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private:
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char data_[kPageSize]; // The cached data.
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static const int kValidityMapSize = kPageSize >> kLineShift;
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char validity_map_[kValidityMapSize]; // One byte per line.
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};
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class SimInstructionBase : public InstructionBase {
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public:
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Type InstructionType() const { return type_; }
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inline Instruction* instr() const { return instr_; }
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inline int32_t operand() const { return operand_; }
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protected:
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SimInstructionBase() : operand_(-1), instr_(nullptr), type_(kUnsupported) {}
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explicit SimInstructionBase(Instruction* instr) {}
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int32_t operand_;
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Instruction* instr_;
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Type type_;
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private:
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DISALLOW_ASSIGN(SimInstructionBase);
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};
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class SimInstruction : public InstructionGetters<SimInstructionBase> {
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public:
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SimInstruction() {}
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explicit SimInstruction(Instruction* instr) { *this = instr; }
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SimInstruction& operator=(Instruction* instr) {
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operand_ = *reinterpret_cast<const int32_t*>(instr);
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instr_ = instr;
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type_ = InstructionBase::InstructionType();
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DCHECK(reinterpret_cast<void*>(&operand_) == this);
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return *this;
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}
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};
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class Simulator : public SimulatorBase {
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public:
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friend class MipsDebugger;
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// Registers are declared in order. See SMRL chapter 2.
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enum Register {
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no_reg = -1,
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zero_reg = 0,
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at,
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v0, v1,
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a0, a1, a2, a3, a4, a5, a6, a7,
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t0, t1, t2, t3,
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s0, s1, s2, s3, s4, s5, s6, s7,
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t8, t9,
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k0, k1,
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gp,
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sp,
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s8,
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ra,
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// LO, HI, and pc.
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LO,
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HI,
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pc, // pc must be the last register.
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kNumSimuRegisters,
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// aliases
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fp = s8
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};
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// Coprocessor registers.
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// Generated code will always use doubles. So we will only use even registers.
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enum FPURegister {
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f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11,
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f12, f13, f14, f15, // f12 and f14 are arguments FPURegisters.
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f16, f17, f18, f19, f20, f21, f22, f23, f24, f25,
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f26, f27, f28, f29, f30, f31,
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kNumFPURegisters
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};
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// MSA registers
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enum MSARegister {
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w0,
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w1,
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w2,
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w3,
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w4,
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w5,
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w6,
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w7,
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w8,
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w9,
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w10,
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w11,
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w12,
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w13,
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w14,
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w15,
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w16,
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w17,
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w18,
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w19,
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w20,
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w21,
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w22,
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w23,
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w24,
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w25,
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w26,
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w27,
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w28,
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w29,
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w30,
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w31,
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kNumMSARegisters
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};
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explicit Simulator(Isolate* isolate);
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~Simulator();
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// The currently executing Simulator instance. Potentially there can be one
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// for each native thread.
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V8_EXPORT_PRIVATE static Simulator* current(v8::internal::Isolate* isolate);
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// Accessors for register state. Reading the pc value adheres to the MIPS
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// architecture specification and is off by a 8 from the currently executing
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// instruction.
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void set_register(int reg, int64_t value);
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void set_register_word(int reg, int32_t value);
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void set_dw_register(int dreg, const int* dbl);
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int64_t get_register(int reg) const;
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double get_double_from_register_pair(int reg);
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// Same for FPURegisters.
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void set_fpu_register(int fpureg, int64_t value);
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void set_fpu_register_word(int fpureg, int32_t value);
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void set_fpu_register_hi_word(int fpureg, int32_t value);
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void set_fpu_register_float(int fpureg, float value);
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void set_fpu_register_double(int fpureg, double value);
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void set_fpu_register_invalid_result64(float original, float rounded);
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void set_fpu_register_invalid_result(float original, float rounded);
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void set_fpu_register_word_invalid_result(float original, float rounded);
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void set_fpu_register_invalid_result64(double original, double rounded);
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void set_fpu_register_invalid_result(double original, double rounded);
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void set_fpu_register_word_invalid_result(double original, double rounded);
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int64_t get_fpu_register(int fpureg) const;
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int32_t get_fpu_register_word(int fpureg) const;
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int32_t get_fpu_register_signed_word(int fpureg) const;
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int32_t get_fpu_register_hi_word(int fpureg) const;
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float get_fpu_register_float(int fpureg) const;
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double get_fpu_register_double(int fpureg) const;
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template <typename T>
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void get_msa_register(int wreg, T* value);
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template <typename T>
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void set_msa_register(int wreg, const T* value);
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void set_fcsr_bit(uint32_t cc, bool value);
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bool test_fcsr_bit(uint32_t cc);
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bool set_fcsr_round_error(double original, double rounded);
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bool set_fcsr_round64_error(double original, double rounded);
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bool set_fcsr_round_error(float original, float rounded);
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bool set_fcsr_round64_error(float original, float rounded);
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void round_according_to_fcsr(double toRound, double& rounded,
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int32_t& rounded_int, double fs);
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void round64_according_to_fcsr(double toRound, double& rounded,
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int64_t& rounded_int, double fs);
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void round_according_to_fcsr(float toRound, float& rounded,
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int32_t& rounded_int, float fs);
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void round64_according_to_fcsr(float toRound, float& rounded,
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int64_t& rounded_int, float fs);
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template <typename T_fp, typename T_int>
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void round_according_to_msacsr(T_fp toRound, T_fp& rounded,
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T_int& rounded_int);
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void set_fcsr_rounding_mode(FPURoundingMode mode);
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void set_msacsr_rounding_mode(FPURoundingMode mode);
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unsigned int get_fcsr_rounding_mode();
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unsigned int get_msacsr_rounding_mode();
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// Special case of set_register and get_register to access the raw PC value.
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void set_pc(int64_t value);
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int64_t get_pc() const;
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Address get_sp() const { return static_cast<Address>(get_register(sp)); }
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// Accessor to the internal simulator stack area.
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uintptr_t StackLimit(uintptr_t c_limit) const;
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// Executes MIPS instructions until the PC reaches end_sim_pc.
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void Execute();
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template <typename Return, typename... Args>
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Return Call(Address entry, Args... args) {
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return VariadicCall<Return>(this, &Simulator::CallImpl, entry, args...);
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}
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// Alternative: call a 2-argument double function.
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double CallFP(Address entry, double d0, double d1);
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// Push an address onto the JS stack.
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uintptr_t PushAddress(uintptr_t address);
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// Pop an address from the JS stack.
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uintptr_t PopAddress();
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// Debugger input.
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void set_last_debugger_input(char* input);
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char* last_debugger_input() { return last_debugger_input_; }
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// Redirection support.
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static void SetRedirectInstruction(Instruction* instruction);
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// ICache checking.
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static bool ICacheMatch(void* one, void* two);
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static void FlushICache(base::CustomMatcherHashMap* i_cache, void* start,
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size_t size);
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// Returns true if pc register contains one of the 'special_values' defined
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// below (bad_ra, end_sim_pc).
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bool has_bad_pc() const;
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private:
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enum special_values {
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// Known bad pc value to ensure that the simulator does not execute
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// without being properly setup.
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bad_ra = -1,
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// A pc value used to signal the simulator to stop execution. Generally
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// the ra is set to this value on transition from native C code to
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// simulated execution, so that the simulator can "return" to the native
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// C code.
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end_sim_pc = -2,
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// Unpredictable value.
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Unpredictable = 0xbadbeaf
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};
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V8_EXPORT_PRIVATE intptr_t CallImpl(Address entry, int argument_count,
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const intptr_t* arguments);
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// Unsupported instructions use Format to print an error and stop execution.
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void Format(Instruction* instr, const char* format);
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// Helpers for data value tracing.
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enum TraceType {
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BYTE,
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HALF,
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WORD,
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DWORD,
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FLOAT,
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DOUBLE,
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FLOAT_DOUBLE,
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WORD_DWORD
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};
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// MSA Data Format
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enum MSADataFormat { MSA_VECT = 0, MSA_BYTE, MSA_HALF, MSA_WORD, MSA_DWORD };
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typedef union {
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int8_t b[kMSALanesByte];
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uint8_t ub[kMSALanesByte];
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int16_t h[kMSALanesHalf];
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uint16_t uh[kMSALanesHalf];
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int32_t w[kMSALanesWord];
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uint32_t uw[kMSALanesWord];
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int64_t d[kMSALanesDword];
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uint64_t ud[kMSALanesDword];
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} msa_reg_t;
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// Read and write memory.
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inline uint32_t ReadBU(int64_t addr);
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inline int32_t ReadB(int64_t addr);
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inline void WriteB(int64_t addr, uint8_t value);
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inline void WriteB(int64_t addr, int8_t value);
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inline uint16_t ReadHU(int64_t addr, Instruction* instr);
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inline int16_t ReadH(int64_t addr, Instruction* instr);
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// Note: Overloaded on the sign of the value.
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inline void WriteH(int64_t addr, uint16_t value, Instruction* instr);
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inline void WriteH(int64_t addr, int16_t value, Instruction* instr);
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inline uint32_t ReadWU(int64_t addr, Instruction* instr);
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inline int32_t ReadW(int64_t addr, Instruction* instr, TraceType t = WORD);
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inline void WriteW(int64_t addr, int32_t value, Instruction* instr);
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inline int64_t Read2W(int64_t addr, Instruction* instr);
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inline void Write2W(int64_t addr, int64_t value, Instruction* instr);
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inline double ReadD(int64_t addr, Instruction* instr);
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inline void WriteD(int64_t addr, double value, Instruction* instr);
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template <typename T>
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T ReadMem(int64_t addr, Instruction* instr);
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template <typename T>
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void WriteMem(int64_t addr, T value, Instruction* instr);
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// Helper for debugging memory access.
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inline void DieOrDebug();
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void TraceRegWr(int64_t value, TraceType t = DWORD);
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template <typename T>
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void TraceMSARegWr(T* value, TraceType t);
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template <typename T>
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void TraceMSARegWr(T* value);
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void TraceMemWr(int64_t addr, int64_t value, TraceType t);
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void TraceMemRd(int64_t addr, int64_t value, TraceType t = DWORD);
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template <typename T>
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void TraceMemRd(int64_t addr, T value);
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template <typename T>
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void TraceMemWr(int64_t addr, T value);
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// Operations depending on endianness.
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// Get Double Higher / Lower word.
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inline int32_t GetDoubleHIW(double* addr);
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inline int32_t GetDoubleLOW(double* addr);
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// Set Double Higher / Lower word.
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inline int32_t SetDoubleHIW(double* addr);
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inline int32_t SetDoubleLOW(double* addr);
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SimInstruction instr_;
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// functions called from DecodeTypeRegister.
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void DecodeTypeRegisterCOP1();
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void DecodeTypeRegisterCOP1X();
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void DecodeTypeRegisterSPECIAL();
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void DecodeTypeRegisterSPECIAL2();
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void DecodeTypeRegisterSPECIAL3();
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void DecodeTypeRegisterSRsType();
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void DecodeTypeRegisterDRsType();
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void DecodeTypeRegisterWRsType();
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void DecodeTypeRegisterLRsType();
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int DecodeMsaDataFormat();
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void DecodeTypeMsaI8();
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void DecodeTypeMsaI5();
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void DecodeTypeMsaI10();
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void DecodeTypeMsaELM();
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void DecodeTypeMsaBIT();
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void DecodeTypeMsaMI10();
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void DecodeTypeMsa3R();
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void DecodeTypeMsa3RF();
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void DecodeTypeMsaVec();
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void DecodeTypeMsa2R();
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void DecodeTypeMsa2RF();
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template <typename T>
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T MsaI5InstrHelper(uint32_t opcode, T ws, int32_t i5);
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template <typename T>
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T MsaBitInstrHelper(uint32_t opcode, T wd, T ws, int32_t m);
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template <typename T>
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T Msa3RInstrHelper(uint32_t opcode, T wd, T ws, T wt);
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// Executing is handled based on the instruction type.
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void DecodeTypeRegister();
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inline int32_t rs_reg() const { return instr_.RsValue(); }
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inline int64_t rs() const { return get_register(rs_reg()); }
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inline uint64_t rs_u() const {
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return static_cast<uint64_t>(get_register(rs_reg()));
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}
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inline int32_t rt_reg() const { return instr_.RtValue(); }
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inline int64_t rt() const { return get_register(rt_reg()); }
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inline uint64_t rt_u() const {
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return static_cast<uint64_t>(get_register(rt_reg()));
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}
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inline int32_t rd_reg() const { return instr_.RdValue(); }
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inline int32_t fr_reg() const { return instr_.FrValue(); }
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inline int32_t fs_reg() const { return instr_.FsValue(); }
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inline int32_t ft_reg() const { return instr_.FtValue(); }
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inline int32_t fd_reg() const { return instr_.FdValue(); }
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inline int32_t sa() const { return instr_.SaValue(); }
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inline int32_t lsa_sa() const { return instr_.LsaSaValue(); }
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inline int32_t ws_reg() const { return instr_.WsValue(); }
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inline int32_t wt_reg() const { return instr_.WtValue(); }
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inline int32_t wd_reg() const { return instr_.WdValue(); }
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inline void SetResult(const int32_t rd_reg, const int64_t alu_out) {
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set_register(rd_reg, alu_out);
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TraceRegWr(alu_out);
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}
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inline void SetFPUWordResult(int32_t fd_reg, int32_t alu_out) {
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set_fpu_register_word(fd_reg, alu_out);
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TraceRegWr(get_fpu_register(fd_reg), WORD);
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}
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inline void SetFPUWordResult2(int32_t fd_reg, int32_t alu_out) {
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set_fpu_register_word(fd_reg, alu_out);
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TraceRegWr(get_fpu_register(fd_reg));
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}
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inline void SetFPUResult(int32_t fd_reg, int64_t alu_out) {
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set_fpu_register(fd_reg, alu_out);
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TraceRegWr(get_fpu_register(fd_reg));
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}
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inline void SetFPUResult2(int32_t fd_reg, int64_t alu_out) {
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set_fpu_register(fd_reg, alu_out);
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TraceRegWr(get_fpu_register(fd_reg), DOUBLE);
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}
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inline void SetFPUFloatResult(int32_t fd_reg, float alu_out) {
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set_fpu_register_float(fd_reg, alu_out);
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TraceRegWr(get_fpu_register(fd_reg), FLOAT);
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}
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inline void SetFPUDoubleResult(int32_t fd_reg, double alu_out) {
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set_fpu_register_double(fd_reg, alu_out);
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TraceRegWr(get_fpu_register(fd_reg), DOUBLE);
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}
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void DecodeTypeImmediate();
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void DecodeTypeJump();
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// Used for breakpoints and traps.
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void SoftwareInterrupt();
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// Compact branch guard.
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void CheckForbiddenSlot(int64_t current_pc) {
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Instruction* instr_after_compact_branch =
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reinterpret_cast<Instruction*>(current_pc + kInstrSize);
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if (instr_after_compact_branch->IsForbiddenAfterBranch()) {
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FATAL(
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"Error: Unexpected instruction 0x%08x immediately after a "
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"compact branch instruction.",
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*reinterpret_cast<uint32_t*>(instr_after_compact_branch));
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}
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}
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// Stop helper functions.
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bool IsWatchpoint(uint64_t code);
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void PrintWatchpoint(uint64_t code);
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void HandleStop(uint64_t code, Instruction* instr);
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bool IsStopInstruction(Instruction* instr);
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bool IsEnabledStop(uint64_t code);
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void EnableStop(uint64_t code);
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void DisableStop(uint64_t code);
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void IncreaseStopCounter(uint64_t code);
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void PrintStopInfo(uint64_t code);
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// Executes one instruction.
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void InstructionDecode(Instruction* instr);
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// Execute one instruction placed in a branch delay slot.
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void BranchDelayInstructionDecode(Instruction* instr) {
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if (instr->InstructionBits() == nopInstr) {
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// Short-cut generic nop instructions. They are always valid and they
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// never change the simulator state.
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return;
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}
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if (instr->IsForbiddenAfterBranch()) {
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FATAL("Eror:Unexpected %i opcode in a branch delay slot.",
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instr->OpcodeValue());
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}
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InstructionDecode(instr);
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SNPrintF(trace_buf_, " ");
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}
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// ICache.
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static void CheckICache(base::CustomMatcherHashMap* i_cache,
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Instruction* instr);
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static void FlushOnePage(base::CustomMatcherHashMap* i_cache, intptr_t start,
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size_t size);
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static CachePage* GetCachePage(base::CustomMatcherHashMap* i_cache,
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void* page);
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enum Exception {
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none,
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kIntegerOverflow,
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kIntegerUnderflow,
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kDivideByZero,
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kNumExceptions
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};
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// Exceptions.
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void SignalException(Exception e);
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// Handle arguments and return value for runtime FP functions.
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void GetFpArgs(double* x, double* y, int32_t* z);
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void SetFpResult(const double& result);
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void CallInternal(Address entry);
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// Architecture state.
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// Registers.
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int64_t registers_[kNumSimuRegisters];
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// Coprocessor Registers.
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// Note: FPUregisters_[] array is increased to 64 * 8B = 32 * 16B in
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// order to support MSA registers
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int64_t FPUregisters_[kNumFPURegisters * 2];
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// FPU control register.
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uint32_t FCSR_;
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// MSA control register.
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uint32_t MSACSR_;
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// Simulator support.
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// Allocate 1MB for stack.
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size_t stack_size_;
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char* stack_;
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bool pc_modified_;
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int64_t icount_;
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int break_count_;
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EmbeddedVector<char, 128> trace_buf_;
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// Debugger input.
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char* last_debugger_input_;
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v8::internal::Isolate* isolate_;
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// Registered breakpoints.
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Instruction* break_pc_;
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Instr break_instr_;
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// Stop is disabled if bit 31 is set.
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static const uint32_t kStopDisabledBit = 1 << 31;
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// A stop is enabled, meaning the simulator will stop when meeting the
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// instruction, if bit 31 of watched_stops_[code].count is unset.
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// The value watched_stops_[code].count & ~(1 << 31) indicates how many times
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// the breakpoint was hit or gone through.
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struct StopCountAndDesc {
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uint32_t count;
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char* desc;
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};
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StopCountAndDesc watched_stops_[kMaxStopCode + 1];
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};
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} // namespace internal
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} // namespace v8
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#endif // defined(USE_SIMULATOR)
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#endif // V8_MIPS64_SIMULATOR_MIPS64_H_
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