// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_COMPILER_INSTRUCTION_CODES_H_
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#define V8_COMPILER_INSTRUCTION_CODES_H_
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#include <iosfwd>
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#if V8_TARGET_ARCH_ARM
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#include "src/compiler/arm/instruction-codes-arm.h"
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#elif V8_TARGET_ARCH_ARM64
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#include "src/compiler/arm64/instruction-codes-arm64.h"
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#elif V8_TARGET_ARCH_IA32
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#include "src/compiler/ia32/instruction-codes-ia32.h"
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#elif V8_TARGET_ARCH_MIPS
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#include "src/compiler/mips/instruction-codes-mips.h"
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#elif V8_TARGET_ARCH_MIPS64
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#include "src/compiler/mips64/instruction-codes-mips64.h"
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#elif V8_TARGET_ARCH_X64
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#include "src/compiler/x64/instruction-codes-x64.h"
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#elif V8_TARGET_ARCH_PPC
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#include "src/compiler/ppc/instruction-codes-ppc.h"
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#elif V8_TARGET_ARCH_S390
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#include "src/compiler/s390/instruction-codes-s390.h"
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#else
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#define TARGET_ARCH_OPCODE_LIST(V)
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#define TARGET_ADDRESSING_MODE_LIST(V)
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#endif
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#include "src/globals.h"
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#include "src/utils.h"
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namespace v8 {
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namespace internal {
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namespace compiler {
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// Modes for ArchStoreWithWriteBarrier below.
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enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny };
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// Target-specific opcodes that specify which assembly sequence to emit.
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// Most opcodes specify a single instruction.
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#define COMMON_ARCH_OPCODE_LIST(V) \
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V(ArchCallCodeObject) \
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V(ArchTailCallCodeObjectFromJSFunction) \
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V(ArchTailCallCodeObject) \
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V(ArchCallJSFunction) \
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V(ArchTailCallAddress) \
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V(ArchPrepareCallCFunction) \
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V(ArchSaveCallerRegisters) \
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V(ArchRestoreCallerRegisters) \
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V(ArchCallCFunction) \
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V(ArchPrepareTailCall) \
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V(ArchCallWasmFunction) \
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V(ArchTailCallWasm) \
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V(ArchJmp) \
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V(ArchBinarySearchSwitch) \
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V(ArchLookupSwitch) \
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V(ArchTableSwitch) \
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V(ArchNop) \
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V(ArchDebugAbort) \
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V(ArchDebugBreak) \
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V(ArchComment) \
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V(ArchThrowTerminator) \
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V(ArchDeoptimize) \
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V(ArchRet) \
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V(ArchStackPointer) \
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V(ArchFramePointer) \
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V(ArchParentFramePointer) \
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V(ArchTruncateDoubleToI) \
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V(ArchStoreWithWriteBarrier) \
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V(ArchStackSlot) \
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V(ArchWordPoisonOnSpeculation) \
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V(Word32AtomicLoadInt8) \
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V(Word32AtomicLoadUint8) \
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V(Word32AtomicLoadInt16) \
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V(Word32AtomicLoadUint16) \
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V(Word32AtomicLoadWord32) \
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V(Word32AtomicStoreWord8) \
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V(Word32AtomicStoreWord16) \
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V(Word32AtomicStoreWord32) \
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V(Word32AtomicExchangeInt8) \
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V(Word32AtomicExchangeUint8) \
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V(Word32AtomicExchangeInt16) \
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V(Word32AtomicExchangeUint16) \
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V(Word32AtomicExchangeWord32) \
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V(Word32AtomicCompareExchangeInt8) \
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V(Word32AtomicCompareExchangeUint8) \
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V(Word32AtomicCompareExchangeInt16) \
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V(Word32AtomicCompareExchangeUint16) \
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V(Word32AtomicCompareExchangeWord32) \
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V(Word32AtomicAddInt8) \
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V(Word32AtomicAddUint8) \
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V(Word32AtomicAddInt16) \
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V(Word32AtomicAddUint16) \
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V(Word32AtomicAddWord32) \
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V(Word32AtomicSubInt8) \
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V(Word32AtomicSubUint8) \
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V(Word32AtomicSubInt16) \
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V(Word32AtomicSubUint16) \
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V(Word32AtomicSubWord32) \
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V(Word32AtomicAndInt8) \
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V(Word32AtomicAndUint8) \
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V(Word32AtomicAndInt16) \
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V(Word32AtomicAndUint16) \
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V(Word32AtomicAndWord32) \
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V(Word32AtomicOrInt8) \
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V(Word32AtomicOrUint8) \
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V(Word32AtomicOrInt16) \
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V(Word32AtomicOrUint16) \
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V(Word32AtomicOrWord32) \
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V(Word32AtomicXorInt8) \
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V(Word32AtomicXorUint8) \
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V(Word32AtomicXorInt16) \
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V(Word32AtomicXorUint16) \
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V(Word32AtomicXorWord32) \
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V(Ieee754Float64Acos) \
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V(Ieee754Float64Acosh) \
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V(Ieee754Float64Asin) \
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V(Ieee754Float64Asinh) \
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V(Ieee754Float64Atan) \
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V(Ieee754Float64Atanh) \
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V(Ieee754Float64Atan2) \
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V(Ieee754Float64Cbrt) \
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V(Ieee754Float64Cos) \
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V(Ieee754Float64Cosh) \
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V(Ieee754Float64Exp) \
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V(Ieee754Float64Expm1) \
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V(Ieee754Float64Log) \
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V(Ieee754Float64Log1p) \
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V(Ieee754Float64Log10) \
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V(Ieee754Float64Log2) \
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V(Ieee754Float64Pow) \
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V(Ieee754Float64Sin) \
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V(Ieee754Float64Sinh) \
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V(Ieee754Float64Tan) \
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V(Ieee754Float64Tanh)
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#define ARCH_OPCODE_LIST(V) \
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COMMON_ARCH_OPCODE_LIST(V) \
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TARGET_ARCH_OPCODE_LIST(V)
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enum ArchOpcode {
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#define DECLARE_ARCH_OPCODE(Name) k##Name,
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ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE)
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#undef DECLARE_ARCH_OPCODE
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#define COUNT_ARCH_OPCODE(Name) +1
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kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE)
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#undef COUNT_ARCH_OPCODE
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};
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V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
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const ArchOpcode& ao);
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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// are encoded into the InstructionCode of the instruction and tell the
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// code generator after register allocation which assembler method to call.
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#define ADDRESSING_MODE_LIST(V) \
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V(None) \
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TARGET_ADDRESSING_MODE_LIST(V)
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enum AddressingMode {
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#define DECLARE_ADDRESSING_MODE(Name) kMode_##Name,
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ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE)
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#undef DECLARE_ADDRESSING_MODE
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#define COUNT_ADDRESSING_MODE(Name) +1
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kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE)
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#undef COUNT_ADDRESSING_MODE
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};
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V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
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const AddressingMode& am);
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// The mode of the flags continuation (see below).
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enum FlagsMode {
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kFlags_none = 0,
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kFlags_branch = 1,
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kFlags_branch_and_poison = 2,
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kFlags_deoptimize = 3,
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kFlags_deoptimize_and_poison = 4,
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kFlags_set = 5,
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kFlags_trap = 6
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};
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V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
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const FlagsMode& fm);
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// The condition of flags continuation (see below).
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enum FlagsCondition {
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kEqual,
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kNotEqual,
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kSignedLessThan,
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kSignedGreaterThanOrEqual,
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kSignedLessThanOrEqual,
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kSignedGreaterThan,
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kUnsignedLessThan,
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kUnsignedGreaterThanOrEqual,
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kUnsignedLessThanOrEqual,
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kUnsignedGreaterThan,
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kFloatLessThanOrUnordered,
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kFloatGreaterThanOrEqual,
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kFloatLessThanOrEqual,
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kFloatGreaterThanOrUnordered,
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kFloatLessThan,
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kFloatGreaterThanOrEqualOrUnordered,
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kFloatLessThanOrEqualOrUnordered,
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kFloatGreaterThan,
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kUnorderedEqual,
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kUnorderedNotEqual,
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kOverflow,
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kNotOverflow,
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kPositiveOrZero,
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kNegative
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};
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inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) {
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return static_cast<FlagsCondition>(condition ^ 1);
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}
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FlagsCondition CommuteFlagsCondition(FlagsCondition condition);
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V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
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const FlagsCondition& fc);
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enum MemoryAccessMode {
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kMemoryAccessDirect = 0,
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kMemoryAccessProtected = 1,
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kMemoryAccessPoisoned = 2
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};
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// The InstructionCode is an opaque, target-specific integer that encodes
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// what code to emit for an instruction in the code generator. It is not
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// interesting to the register allocator, as the inputs and flags on the
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// instructions specify everything of interest.
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typedef int32_t InstructionCode;
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// Helpers for encoding / decoding InstructionCode into the fields needed
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// for code generation. We encode the instruction, addressing mode, and flags
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// continuation into a single InstructionCode which is stored as part of
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// the instruction.
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typedef BitField<ArchOpcode, 0, 9> ArchOpcodeField;
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typedef BitField<AddressingMode, 9, 5> AddressingModeField;
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typedef BitField<FlagsMode, 14, 3> FlagsModeField;
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typedef BitField<FlagsCondition, 17, 5> FlagsConditionField;
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typedef BitField<int, 22, 10> MiscField;
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} // namespace compiler
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} // namespace internal
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} // namespace v8
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#endif // V8_COMPILER_INSTRUCTION_CODES_H_
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