// Copyright 2006-2013 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// This module contains the architecture-specific code. This make the rest of
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// the code less dependent on differences between different processor
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// architecture.
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// The classes have the same definition for all architectures. The
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// implementation for a particular architecture is put in cpu_<arch>.cc.
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// The build system then uses the implementation for the target architecture.
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//
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#ifndef V8_BASE_CPU_H_
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#define V8_BASE_CPU_H_
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#include "src/base/base-export.h"
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#include "src/base/macros.h"
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namespace v8 {
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namespace base {
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// ----------------------------------------------------------------------------
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// CPU
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//
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// Query information about the processor.
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//
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// This class also has static methods for the architecture specific functions.
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// Add methods here to cope with differences between the supported
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// architectures. For each architecture the file cpu_<arch>.cc contains the
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// implementation of these static functions.
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class V8_BASE_EXPORT CPU final {
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public:
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CPU();
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// x86 CPUID information
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const char* vendor() const { return vendor_; }
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int stepping() const { return stepping_; }
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int model() const { return model_; }
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int ext_model() const { return ext_model_; }
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int family() const { return family_; }
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int ext_family() const { return ext_family_; }
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int type() const { return type_; }
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// arm implementer/part information
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int implementer() const { return implementer_; }
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static const int ARM = 0x41;
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static const int NVIDIA = 0x4e;
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static const int QUALCOMM = 0x51;
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int architecture() const { return architecture_; }
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int variant() const { return variant_; }
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static const int NVIDIA_DENVER = 0x0;
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int part() const { return part_; }
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// ARM-specific part codes
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static const int ARM_CORTEX_A5 = 0xc05;
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static const int ARM_CORTEX_A7 = 0xc07;
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static const int ARM_CORTEX_A8 = 0xc08;
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static const int ARM_CORTEX_A9 = 0xc09;
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static const int ARM_CORTEX_A12 = 0xc0c;
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static const int ARM_CORTEX_A15 = 0xc0f;
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// Denver-specific part code
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static const int NVIDIA_DENVER_V10 = 0x002;
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// PPC-specific part codes
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enum {
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PPC_POWER5,
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PPC_POWER6,
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PPC_POWER7,
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PPC_POWER8,
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PPC_POWER9,
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PPC_G4,
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PPC_G5,
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PPC_PA6T
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};
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// General features
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bool has_fpu() const { return has_fpu_; }
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int icache_line_size() const { return icache_line_size_; }
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int dcache_line_size() const { return dcache_line_size_; }
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static const int UNKNOWN_CACHE_LINE_SIZE = 0;
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// x86 features
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bool has_cmov() const { return has_cmov_; }
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bool has_sahf() const { return has_sahf_; }
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bool has_mmx() const { return has_mmx_; }
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bool has_sse() const { return has_sse_; }
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bool has_sse2() const { return has_sse2_; }
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bool has_sse3() const { return has_sse3_; }
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bool has_ssse3() const { return has_ssse3_; }
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bool has_sse41() const { return has_sse41_; }
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bool has_sse42() const { return has_sse42_; }
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bool has_osxsave() const { return has_osxsave_; }
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bool has_avx() const { return has_avx_; }
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bool has_fma3() const { return has_fma3_; }
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bool has_bmi1() const { return has_bmi1_; }
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bool has_bmi2() const { return has_bmi2_; }
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bool has_lzcnt() const { return has_lzcnt_; }
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bool has_popcnt() const { return has_popcnt_; }
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bool is_atom() const { return is_atom_; }
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bool has_non_stop_time_stamp_counter() const {
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return has_non_stop_time_stamp_counter_;
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}
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// arm features
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bool has_idiva() const { return has_idiva_; }
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bool has_neon() const { return has_neon_; }
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bool has_thumb2() const { return has_thumb2_; }
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bool has_vfp() const { return has_vfp_; }
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bool has_vfp3() const { return has_vfp3_; }
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bool has_vfp3_d32() const { return has_vfp3_d32_; }
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// mips features
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bool is_fp64_mode() const { return is_fp64_mode_; }
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bool has_msa() const { return has_msa_; }
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private:
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char vendor_[13];
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int stepping_;
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int model_;
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int ext_model_;
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int family_;
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int ext_family_;
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int type_;
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int implementer_;
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int architecture_;
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int variant_;
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int part_;
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int icache_line_size_;
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int dcache_line_size_;
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bool has_fpu_;
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bool has_cmov_;
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bool has_sahf_;
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bool has_mmx_;
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bool has_sse_;
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bool has_sse2_;
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bool has_sse3_;
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bool has_ssse3_;
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bool has_sse41_;
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bool has_sse42_;
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bool is_atom_;
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bool has_osxsave_;
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bool has_avx_;
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bool has_fma3_;
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bool has_bmi1_;
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bool has_bmi2_;
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bool has_lzcnt_;
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bool has_popcnt_;
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bool has_idiva_;
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bool has_neon_;
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bool has_thumb2_;
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bool has_vfp_;
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bool has_vfp3_;
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bool has_vfp3_d32_;
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bool is_fp64_mode_;
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bool has_non_stop_time_stamp_counter_;
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bool has_msa_;
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};
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} // namespace base
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} // namespace v8
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#endif // V8_BASE_CPU_H_
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