// Copyright 2013 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
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#define V8_ARM64_ASSEMBLER_ARM64_INL_H_
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#include "src/arm64/assembler-arm64.h"
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#include "src/assembler.h"
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#include "src/debug/debug.h"
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#include "src/objects-inl.h"
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namespace v8 {
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namespace internal {
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bool CpuFeatures::SupportsOptimizer() { return true; }
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bool CpuFeatures::SupportsWasmSimd128() { return true; }
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void RelocInfo::apply(intptr_t delta) {
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// On arm64 only internal references and immediate branches need extra work.
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if (RelocInfo::IsInternalReference(rmode_)) {
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// Absolute code pointer inside code object moves with the code object.
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intptr_t* p = reinterpret_cast<intptr_t*>(pc_);
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*p += delta; // Relocate entry.
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} else {
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Instruction* instr = reinterpret_cast<Instruction*>(pc_);
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if (instr->IsBranchAndLink() || instr->IsUnconditionalBranch()) {
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Address old_target =
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reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
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Address new_target = old_target - delta;
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instr->SetBranchImmTarget(reinterpret_cast<Instruction*>(new_target));
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}
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}
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}
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inline bool CPURegister::IsSameSizeAndType(const CPURegister& other) const {
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return (reg_size_ == other.reg_size_) && (reg_type_ == other.reg_type_);
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}
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inline bool CPURegister::IsZero() const {
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DCHECK(IsValid());
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return IsRegister() && (reg_code_ == kZeroRegCode);
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}
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inline bool CPURegister::IsSP() const {
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DCHECK(IsValid());
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return IsRegister() && (reg_code_ == kSPRegInternalCode);
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}
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inline void CPURegList::Combine(const CPURegList& other) {
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DCHECK(IsValid());
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DCHECK(other.type() == type_);
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DCHECK(other.RegisterSizeInBits() == size_);
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list_ |= other.list();
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}
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inline void CPURegList::Remove(const CPURegList& other) {
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DCHECK(IsValid());
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if (other.type() == type_) {
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list_ &= ~other.list();
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}
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}
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inline void CPURegList::Combine(const CPURegister& other) {
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DCHECK(other.type() == type_);
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DCHECK(other.SizeInBits() == size_);
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Combine(other.code());
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}
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inline void CPURegList::Remove(const CPURegister& other1,
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const CPURegister& other2,
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const CPURegister& other3,
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const CPURegister& other4) {
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if (!other1.IsNone() && (other1.type() == type_)) Remove(other1.code());
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if (!other2.IsNone() && (other2.type() == type_)) Remove(other2.code());
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if (!other3.IsNone() && (other3.type() == type_)) Remove(other3.code());
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if (!other4.IsNone() && (other4.type() == type_)) Remove(other4.code());
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}
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inline void CPURegList::Combine(int code) {
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DCHECK(IsValid());
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DCHECK(CPURegister::Create(code, size_, type_).IsValid());
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list_ |= (1UL << code);
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}
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inline void CPURegList::Remove(int code) {
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DCHECK(IsValid());
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DCHECK(CPURegister::Create(code, size_, type_).IsValid());
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list_ &= ~(1UL << code);
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}
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inline Register Register::XRegFromCode(unsigned code) {
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if (code == kSPRegInternalCode) {
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return sp;
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} else {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfRegisters));
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return Register::Create(code, kXRegSizeInBits);
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}
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}
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inline Register Register::WRegFromCode(unsigned code) {
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if (code == kSPRegInternalCode) {
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return wsp;
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} else {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfRegisters));
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return Register::Create(code, kWRegSizeInBits);
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}
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}
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inline VRegister VRegister::BRegFromCode(unsigned code) {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfVRegisters));
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return VRegister::Create(code, kBRegSizeInBits);
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}
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inline VRegister VRegister::HRegFromCode(unsigned code) {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfVRegisters));
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return VRegister::Create(code, kHRegSizeInBits);
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}
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inline VRegister VRegister::SRegFromCode(unsigned code) {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfVRegisters));
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return VRegister::Create(code, kSRegSizeInBits);
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}
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inline VRegister VRegister::DRegFromCode(unsigned code) {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfVRegisters));
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return VRegister::Create(code, kDRegSizeInBits);
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}
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inline VRegister VRegister::QRegFromCode(unsigned code) {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfVRegisters));
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return VRegister::Create(code, kQRegSizeInBits);
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}
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inline VRegister VRegister::VRegFromCode(unsigned code) {
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DCHECK_LT(code, static_cast<unsigned>(kNumberOfVRegisters));
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return VRegister::Create(code, kVRegSizeInBits);
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}
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inline Register CPURegister::W() const {
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DCHECK(IsRegister());
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return Register::WRegFromCode(reg_code_);
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}
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inline Register CPURegister::Reg() const {
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DCHECK(IsRegister());
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return Register::Create(reg_code_, reg_size_);
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}
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inline VRegister CPURegister::VReg() const {
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DCHECK(IsVRegister());
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return VRegister::Create(reg_code_, reg_size_);
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}
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inline Register CPURegister::X() const {
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DCHECK(IsRegister());
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return Register::XRegFromCode(reg_code_);
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}
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inline VRegister CPURegister::V() const {
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DCHECK(IsVRegister());
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return VRegister::VRegFromCode(reg_code_);
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}
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inline VRegister CPURegister::B() const {
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DCHECK(IsVRegister());
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return VRegister::BRegFromCode(reg_code_);
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}
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inline VRegister CPURegister::H() const {
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DCHECK(IsVRegister());
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return VRegister::HRegFromCode(reg_code_);
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}
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inline VRegister CPURegister::S() const {
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DCHECK(IsVRegister());
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return VRegister::SRegFromCode(reg_code_);
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}
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inline VRegister CPURegister::D() const {
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DCHECK(IsVRegister());
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return VRegister::DRegFromCode(reg_code_);
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}
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inline VRegister CPURegister::Q() const {
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DCHECK(IsVRegister());
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return VRegister::QRegFromCode(reg_code_);
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}
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// Immediate.
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// Default initializer is for int types
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template<typename T>
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struct ImmediateInitializer {
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static const bool kIsIntType = true;
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static inline RelocInfo::Mode rmode_for(T) { return RelocInfo::NONE; }
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static inline int64_t immediate_for(T t) {
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STATIC_ASSERT(sizeof(T) <= 8);
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return t;
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}
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};
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template<>
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struct ImmediateInitializer<Smi*> {
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static const bool kIsIntType = false;
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static inline RelocInfo::Mode rmode_for(Smi* t) { return RelocInfo::NONE; }
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static inline int64_t immediate_for(Smi* t) {;
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return reinterpret_cast<int64_t>(t);
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}
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};
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template<>
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struct ImmediateInitializer<ExternalReference> {
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static const bool kIsIntType = false;
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static inline RelocInfo::Mode rmode_for(ExternalReference t) {
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return RelocInfo::EXTERNAL_REFERENCE;
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}
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static inline int64_t immediate_for(ExternalReference t) {;
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return static_cast<int64_t>(t.address());
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}
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};
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template<typename T>
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Immediate::Immediate(Handle<T> value) {
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InitializeHandle(value);
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}
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template<typename T>
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Immediate::Immediate(T t)
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: value_(ImmediateInitializer<T>::immediate_for(t)),
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rmode_(ImmediateInitializer<T>::rmode_for(t)) {}
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template<typename T>
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Immediate::Immediate(T t, RelocInfo::Mode rmode)
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: value_(ImmediateInitializer<T>::immediate_for(t)),
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rmode_(rmode) {
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STATIC_ASSERT(ImmediateInitializer<T>::kIsIntType);
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}
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// Operand.
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template<typename T>
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Operand::Operand(Handle<T> value) : immediate_(value), reg_(NoReg) {}
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template<typename T>
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Operand::Operand(T t) : immediate_(t), reg_(NoReg) {}
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template<typename T>
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Operand::Operand(T t, RelocInfo::Mode rmode)
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: immediate_(t, rmode),
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reg_(NoReg) {}
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Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
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: immediate_(0),
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reg_(reg),
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shift_(shift),
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extend_(NO_EXTEND),
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shift_amount_(shift_amount) {
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DCHECK(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
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DCHECK(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
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DCHECK_IMPLIES(reg.IsSP(), shift_amount == 0);
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}
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Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
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: immediate_(0),
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reg_(reg),
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shift_(NO_SHIFT),
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extend_(extend),
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shift_amount_(shift_amount) {
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DCHECK(reg.IsValid());
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DCHECK_LE(shift_amount, 4);
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DCHECK(!reg.IsSP());
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// Extend modes SXTX and UXTX require a 64-bit register.
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DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
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}
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bool Operand::IsHeapObjectRequest() const {
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DCHECK_IMPLIES(heap_object_request_.has_value(), reg_.Is(NoReg));
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DCHECK_IMPLIES(heap_object_request_.has_value(),
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immediate_.rmode() == RelocInfo::EMBEDDED_OBJECT ||
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immediate_.rmode() == RelocInfo::CODE_TARGET);
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return heap_object_request_.has_value();
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}
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HeapObjectRequest Operand::heap_object_request() const {
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DCHECK(IsHeapObjectRequest());
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return *heap_object_request_;
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}
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bool Operand::IsImmediate() const {
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return reg_.Is(NoReg) && !IsHeapObjectRequest();
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}
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bool Operand::IsShiftedRegister() const {
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return reg_.IsValid() && (shift_ != NO_SHIFT);
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}
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bool Operand::IsExtendedRegister() const {
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return reg_.IsValid() && (extend_ != NO_EXTEND);
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}
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bool Operand::IsZero() const {
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if (IsImmediate()) {
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return ImmediateValue() == 0;
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} else {
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return reg().IsZero();
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}
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}
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Operand Operand::ToExtendedRegister() const {
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DCHECK(IsShiftedRegister());
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DCHECK((shift_ == LSL) && (shift_amount_ <= 4));
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return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
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}
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Immediate Operand::immediate_for_heap_object_request() const {
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DCHECK((heap_object_request().kind() == HeapObjectRequest::kHeapNumber &&
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immediate_.rmode() == RelocInfo::EMBEDDED_OBJECT) ||
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(heap_object_request().kind() == HeapObjectRequest::kCodeStub &&
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immediate_.rmode() == RelocInfo::CODE_TARGET));
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return immediate_;
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}
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Immediate Operand::immediate() const {
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DCHECK(IsImmediate());
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return immediate_;
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}
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int64_t Operand::ImmediateValue() const {
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DCHECK(IsImmediate());
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return immediate_.value();
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}
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RelocInfo::Mode Operand::ImmediateRMode() const {
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DCHECK(IsImmediate() || IsHeapObjectRequest());
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return immediate_.rmode();
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}
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Register Operand::reg() const {
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DCHECK(IsShiftedRegister() || IsExtendedRegister());
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return reg_;
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}
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Shift Operand::shift() const {
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DCHECK(IsShiftedRegister());
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return shift_;
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}
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Extend Operand::extend() const {
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DCHECK(IsExtendedRegister());
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return extend_;
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}
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unsigned Operand::shift_amount() const {
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DCHECK(IsShiftedRegister() || IsExtendedRegister());
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return shift_amount_;
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}
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Operand Operand::UntagSmi(Register smi) {
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DCHECK(smi.Is64Bits());
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DCHECK(SmiValuesAre32Bits() || SmiValuesAre31Bits());
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return Operand(smi, ASR, kSmiShift);
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}
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Operand Operand::UntagSmiAndScale(Register smi, int scale) {
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DCHECK(smi.Is64Bits());
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DCHECK((scale >= 0) && (scale <= (64 - kSmiValueSize)));
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DCHECK(SmiValuesAre32Bits() || SmiValuesAre31Bits());
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if (scale > kSmiShift) {
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return Operand(smi, LSL, scale - kSmiShift);
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} else if (scale < kSmiShift) {
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return Operand(smi, ASR, kSmiShift - scale);
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}
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return Operand(smi);
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}
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MemOperand::MemOperand()
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: base_(NoReg), regoffset_(NoReg), offset_(0), addrmode_(Offset),
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shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
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}
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MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
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: base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode),
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shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
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DCHECK(base.Is64Bits() && !base.IsZero());
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}
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MemOperand::MemOperand(Register base,
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Register regoffset,
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Extend extend,
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unsigned shift_amount)
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: base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
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shift_(NO_SHIFT), extend_(extend), shift_amount_(shift_amount) {
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DCHECK(base.Is64Bits() && !base.IsZero());
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DCHECK(!regoffset.IsSP());
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DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
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// SXTX extend mode requires a 64-bit offset register.
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DCHECK(regoffset.Is64Bits() || (extend != SXTX));
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}
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MemOperand::MemOperand(Register base,
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Register regoffset,
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Shift shift,
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unsigned shift_amount)
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: base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
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shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) {
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DCHECK(base.Is64Bits() && !base.IsZero());
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DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());
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DCHECK(shift == LSL);
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}
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MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
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: base_(base), regoffset_(NoReg), addrmode_(addrmode) {
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DCHECK(base.Is64Bits() && !base.IsZero());
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if (offset.IsImmediate()) {
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offset_ = offset.ImmediateValue();
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} else if (offset.IsShiftedRegister()) {
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DCHECK((addrmode == Offset) || (addrmode == PostIndex));
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regoffset_ = offset.reg();
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shift_ = offset.shift();
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shift_amount_ = offset.shift_amount();
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extend_ = NO_EXTEND;
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offset_ = 0;
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// These assertions match those in the shifted-register constructor.
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DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP());
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DCHECK(shift_ == LSL);
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} else {
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DCHECK(offset.IsExtendedRegister());
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DCHECK(addrmode == Offset);
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regoffset_ = offset.reg();
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extend_ = offset.extend();
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shift_amount_ = offset.shift_amount();
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shift_ = NO_SHIFT;
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offset_ = 0;
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// These assertions match those in the extended-register constructor.
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DCHECK(!regoffset_.IsSP());
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DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
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}
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}
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bool MemOperand::IsImmediateOffset() const {
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return (addrmode_ == Offset) && regoffset_.Is(NoReg);
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}
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bool MemOperand::IsRegisterOffset() const {
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return (addrmode_ == Offset) && !regoffset_.Is(NoReg);
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}
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bool MemOperand::IsPreIndex() const {
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return addrmode_ == PreIndex;
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}
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bool MemOperand::IsPostIndex() const {
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return addrmode_ == PostIndex;
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}
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Operand MemOperand::OffsetAsOperand() const {
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if (IsImmediateOffset()) {
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return offset();
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} else {
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DCHECK(IsRegisterOffset());
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if (extend() == NO_EXTEND) {
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return Operand(regoffset(), shift(), shift_amount());
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} else {
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return Operand(regoffset(), extend(), shift_amount());
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}
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}
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}
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void Assembler::Unreachable() {
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#ifdef USE_SIMULATOR
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debug("UNREACHABLE", __LINE__, BREAK);
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#else
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// Crash by branching to 0. lr now points near the fault.
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Emit(BLR | Rn(xzr));
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#endif
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}
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Address Assembler::target_pointer_address_at(Address pc) {
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Instruction* instr = reinterpret_cast<Instruction*>(pc);
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DCHECK(instr->IsLdrLiteralX());
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return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
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}
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// Read/Modify the code target address in the branch/call instruction at pc.
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Address Assembler::target_address_at(Address pc, Address constant_pool) {
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Instruction* instr = reinterpret_cast<Instruction*>(pc);
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if (instr->IsLdrLiteralX()) {
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return Memory<Address>(target_pointer_address_at(pc));
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} else {
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DCHECK(instr->IsBranchAndLink() || instr->IsUnconditionalBranch());
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return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
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}
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}
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Handle<Code> Assembler::code_target_object_handle_at(Address pc) {
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Instruction* instr = reinterpret_cast<Instruction*>(pc);
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if (instr->IsLdrLiteralX()) {
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return Handle<Code>(reinterpret_cast<Code**>(
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Assembler::target_address_at(pc, 0 /* unused */)));
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} else {
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DCHECK(instr->IsBranchAndLink() || instr->IsUnconditionalBranch());
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DCHECK_EQ(instr->ImmPCOffset() % kInstrSize, 0);
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return GetCodeTarget(instr->ImmPCOffset() >> kInstrSizeLog2);
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}
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}
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Address Assembler::runtime_entry_at(Address pc) {
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Instruction* instr = reinterpret_cast<Instruction*>(pc);
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if (instr->IsLdrLiteralX()) {
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return Assembler::target_address_at(pc, 0 /* unused */);
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} else {
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DCHECK(instr->IsBranchAndLink() || instr->IsUnconditionalBranch());
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return instr->ImmPCOffset() + options().code_range_start;
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}
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}
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Address Assembler::target_address_from_return_address(Address pc) {
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// Returns the address of the call target from the return address that will
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// be returned to after a call.
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// Call sequence on ARM64 is:
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// ldr ip0, #... @ load from literal pool
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// blr ip0
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Address candidate = pc - 2 * kInstrSize;
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Instruction* instr = reinterpret_cast<Instruction*>(candidate);
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USE(instr);
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DCHECK(instr->IsLdrLiteralX());
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return candidate;
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}
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int Assembler::deserialization_special_target_size(Address location) {
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Instruction* instr = reinterpret_cast<Instruction*>(location);
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if (instr->IsBranchAndLink() || instr->IsUnconditionalBranch()) {
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return kSpecialTargetSize;
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} else {
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DCHECK_EQ(instr->InstructionBits(), 0);
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return kPointerSize;
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}
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}
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void Assembler::deserialization_set_special_target_at(Address location,
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Code* code,
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Address target) {
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Instruction* instr = reinterpret_cast<Instruction*>(location);
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if (instr->IsBranchAndLink() || instr->IsUnconditionalBranch()) {
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if (target == 0) {
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// We are simply wiping the target out for serialization. Set the offset
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// to zero instead.
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target = location;
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}
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instr->SetBranchImmTarget(reinterpret_cast<Instruction*>(target));
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Assembler::FlushICache(location, kInstrSize);
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} else {
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DCHECK_EQ(instr->InstructionBits(), 0);
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Memory<Address>(location) = target;
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// Intuitively, we would think it is necessary to always flush the
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// instruction cache after patching a target address in the code. However,
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// in this case, only the constant pool contents change. The instruction
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// accessing the constant pool remains unchanged, so a flush is not
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// required.
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}
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}
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void Assembler::deserialization_set_target_internal_reference_at(
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Address pc, Address target, RelocInfo::Mode mode) {
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Memory<Address>(pc) = target;
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}
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void Assembler::set_target_address_at(Address pc, Address constant_pool,
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Address target,
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ICacheFlushMode icache_flush_mode) {
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Instruction* instr = reinterpret_cast<Instruction*>(pc);
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if (instr->IsLdrLiteralX()) {
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Memory<Address>(target_pointer_address_at(pc)) = target;
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// Intuitively, we would think it is necessary to always flush the
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// instruction cache after patching a target address in the code. However,
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// in this case, only the constant pool contents change. The instruction
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// accessing the constant pool remains unchanged, so a flush is not
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// required.
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} else {
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DCHECK(instr->IsBranchAndLink() || instr->IsUnconditionalBranch());
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if (target == 0) {
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// We are simply wiping the target out for serialization. Set the offset
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// to zero instead.
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target = pc;
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}
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instr->SetBranchImmTarget(reinterpret_cast<Instruction*>(target));
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if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
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Assembler::FlushICache(pc, kInstrSize);
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}
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}
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}
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int RelocInfo::target_address_size() {
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if (IsCodedSpecially()) {
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return Assembler::kSpecialTargetSize;
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} else {
|
DCHECK(reinterpret_cast<Instruction*>(pc_)->IsLdrLiteralX());
|
return kPointerSize;
|
}
|
}
|
|
|
Address RelocInfo::target_address() {
|
DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_) || IsWasmCall(rmode_));
|
return Assembler::target_address_at(pc_, constant_pool_);
|
}
|
|
Address RelocInfo::target_address_address() {
|
DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_) || IsWasmCall(rmode_) ||
|
IsEmbeddedObject(rmode_) || IsExternalReference(rmode_) ||
|
IsOffHeapTarget(rmode_));
|
Instruction* instr = reinterpret_cast<Instruction*>(pc_);
|
// Read the address of the word containing the target_address in an
|
// instruction stream.
|
// The only architecture-independent user of this function is the serializer.
|
// The serializer uses it to find out how many raw bytes of instruction to
|
// output before the next target.
|
// For an instruction like B/BL, where the target bits are mixed into the
|
// instruction bits, the size of the target will be zero, indicating that the
|
// serializer should not step forward in memory after a target is resolved
|
// and written.
|
// For LDR literal instructions, we can skip up to the constant pool entry
|
// address. We make sure that RelocInfo is ordered by the
|
// target_address_address so that we do not skip over any relocatable
|
// instruction sequences.
|
if (instr->IsLdrLiteralX()) {
|
return constant_pool_entry_address();
|
} else {
|
DCHECK(instr->IsBranchAndLink() || instr->IsUnconditionalBranch());
|
return reinterpret_cast<Address>(pc_);
|
}
|
}
|
|
|
Address RelocInfo::constant_pool_entry_address() {
|
DCHECK(IsInConstantPool());
|
return Assembler::target_pointer_address_at(pc_);
|
}
|
|
HeapObject* RelocInfo::target_object() {
|
DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
|
return HeapObject::cast(reinterpret_cast<Object*>(
|
Assembler::target_address_at(pc_, constant_pool_)));
|
}
|
|
Handle<HeapObject> RelocInfo::target_object_handle(Assembler* origin) {
|
if (rmode_ == EMBEDDED_OBJECT) {
|
return Handle<HeapObject>(reinterpret_cast<HeapObject**>(
|
Assembler::target_address_at(pc_, constant_pool_)));
|
} else {
|
DCHECK(IsCodeTarget(rmode_));
|
return origin->code_target_object_handle_at(pc_);
|
}
|
}
|
|
void RelocInfo::set_target_object(Heap* heap, HeapObject* target,
|
WriteBarrierMode write_barrier_mode,
|
ICacheFlushMode icache_flush_mode) {
|
DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
|
Assembler::set_target_address_at(pc_, constant_pool_,
|
reinterpret_cast<Address>(target),
|
icache_flush_mode);
|
if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != nullptr) {
|
WriteBarrierForCode(host(), this, target);
|
}
|
}
|
|
|
Address RelocInfo::target_external_reference() {
|
DCHECK(rmode_ == EXTERNAL_REFERENCE);
|
return Assembler::target_address_at(pc_, constant_pool_);
|
}
|
|
void RelocInfo::set_target_external_reference(
|
Address target, ICacheFlushMode icache_flush_mode) {
|
DCHECK(rmode_ == RelocInfo::EXTERNAL_REFERENCE);
|
Assembler::set_target_address_at(pc_, constant_pool_, target,
|
icache_flush_mode);
|
}
|
|
Address RelocInfo::target_internal_reference() {
|
DCHECK(rmode_ == INTERNAL_REFERENCE);
|
return Memory<Address>(pc_);
|
}
|
|
|
Address RelocInfo::target_internal_reference_address() {
|
DCHECK(rmode_ == INTERNAL_REFERENCE);
|
return pc_;
|
}
|
|
Address RelocInfo::target_runtime_entry(Assembler* origin) {
|
DCHECK(IsRuntimeEntry(rmode_));
|
return origin->runtime_entry_at(pc_);
|
}
|
|
void RelocInfo::set_target_runtime_entry(Address target,
|
WriteBarrierMode write_barrier_mode,
|
ICacheFlushMode icache_flush_mode) {
|
DCHECK(IsRuntimeEntry(rmode_));
|
if (target_address() != target) {
|
set_target_address(target, write_barrier_mode, icache_flush_mode);
|
}
|
}
|
|
Address RelocInfo::target_off_heap_target() {
|
DCHECK(IsOffHeapTarget(rmode_));
|
return Assembler::target_address_at(pc_, constant_pool_);
|
}
|
|
void RelocInfo::WipeOut() {
|
DCHECK(IsEmbeddedObject(rmode_) || IsCodeTarget(rmode_) ||
|
IsRuntimeEntry(rmode_) || IsExternalReference(rmode_) ||
|
IsInternalReference(rmode_) || IsOffHeapTarget(rmode_));
|
if (IsInternalReference(rmode_)) {
|
Memory<Address>(pc_) = kNullAddress;
|
} else {
|
Assembler::set_target_address_at(pc_, constant_pool_, kNullAddress);
|
}
|
}
|
|
template <typename ObjectVisitor>
|
void RelocInfo::Visit(ObjectVisitor* visitor) {
|
RelocInfo::Mode mode = rmode();
|
if (mode == RelocInfo::EMBEDDED_OBJECT) {
|
visitor->VisitEmbeddedPointer(host(), this);
|
} else if (RelocInfo::IsCodeTargetMode(mode)) {
|
visitor->VisitCodeTarget(host(), this);
|
} else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
|
visitor->VisitExternalReference(host(), this);
|
} else if (mode == RelocInfo::INTERNAL_REFERENCE) {
|
visitor->VisitInternalReference(host(), this);
|
} else if (RelocInfo::IsRuntimeEntry(mode)) {
|
visitor->VisitRuntimeEntry(host(), this);
|
} else if (RelocInfo::IsOffHeapTarget(mode)) {
|
visitor->VisitOffHeapTarget(host(), this);
|
}
|
}
|
|
LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
|
DCHECK(rt.IsValid());
|
if (rt.IsRegister()) {
|
return rt.Is64Bits() ? LDR_x : LDR_w;
|
} else {
|
DCHECK(rt.IsVRegister());
|
switch (rt.SizeInBits()) {
|
case kBRegSizeInBits:
|
return LDR_b;
|
case kHRegSizeInBits:
|
return LDR_h;
|
case kSRegSizeInBits:
|
return LDR_s;
|
case kDRegSizeInBits:
|
return LDR_d;
|
default:
|
DCHECK(rt.IsQ());
|
return LDR_q;
|
}
|
}
|
}
|
|
|
LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
|
DCHECK(rt.IsValid());
|
if (rt.IsRegister()) {
|
return rt.Is64Bits() ? STR_x : STR_w;
|
} else {
|
DCHECK(rt.IsVRegister());
|
switch (rt.SizeInBits()) {
|
case kBRegSizeInBits:
|
return STR_b;
|
case kHRegSizeInBits:
|
return STR_h;
|
case kSRegSizeInBits:
|
return STR_s;
|
case kDRegSizeInBits:
|
return STR_d;
|
default:
|
DCHECK(rt.IsQ());
|
return STR_q;
|
}
|
}
|
}
|
|
LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt,
|
const CPURegister& rt2) {
|
DCHECK_EQ(STP_w | LoadStorePairLBit, LDP_w);
|
return static_cast<LoadStorePairOp>(StorePairOpFor(rt, rt2) |
|
LoadStorePairLBit);
|
}
|
|
LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
|
const CPURegister& rt2) {
|
DCHECK(AreSameSizeAndType(rt, rt2));
|
USE(rt2);
|
if (rt.IsRegister()) {
|
return rt.Is64Bits() ? STP_x : STP_w;
|
} else {
|
DCHECK(rt.IsVRegister());
|
switch (rt.SizeInBits()) {
|
case kSRegSizeInBits:
|
return STP_s;
|
case kDRegSizeInBits:
|
return STP_d;
|
default:
|
DCHECK(rt.IsQ());
|
return STP_q;
|
}
|
}
|
}
|
|
|
LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) {
|
if (rt.IsRegister()) {
|
return rt.Is64Bits() ? LDR_x_lit : LDR_w_lit;
|
} else {
|
DCHECK(rt.IsVRegister());
|
return rt.Is64Bits() ? LDR_d_lit : LDR_s_lit;
|
}
|
}
|
|
|
int Assembler::LinkAndGetInstructionOffsetTo(Label* label) {
|
DCHECK_EQ(kStartOfLabelLinkChain, 0);
|
int offset = LinkAndGetByteOffsetTo(label);
|
DCHECK(IsAligned(offset, kInstrSize));
|
return offset >> kInstrSizeLog2;
|
}
|
|
|
Instr Assembler::Flags(FlagsUpdate S) {
|
if (S == SetFlags) {
|
return 1 << FlagsUpdate_offset;
|
} else if (S == LeaveFlags) {
|
return 0 << FlagsUpdate_offset;
|
}
|
UNREACHABLE();
|
}
|
|
|
Instr Assembler::Cond(Condition cond) {
|
return cond << Condition_offset;
|
}
|
|
|
Instr Assembler::ImmPCRelAddress(int imm21) {
|
CHECK(is_int21(imm21));
|
Instr imm = static_cast<Instr>(truncate_to_int21(imm21));
|
Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset;
|
Instr immlo = imm << ImmPCRelLo_offset;
|
return (immhi & ImmPCRelHi_mask) | (immlo & ImmPCRelLo_mask);
|
}
|
|
|
Instr Assembler::ImmUncondBranch(int imm26) {
|
CHECK(is_int26(imm26));
|
return truncate_to_int26(imm26) << ImmUncondBranch_offset;
|
}
|
|
|
Instr Assembler::ImmCondBranch(int imm19) {
|
CHECK(is_int19(imm19));
|
return truncate_to_int19(imm19) << ImmCondBranch_offset;
|
}
|
|
|
Instr Assembler::ImmCmpBranch(int imm19) {
|
CHECK(is_int19(imm19));
|
return truncate_to_int19(imm19) << ImmCmpBranch_offset;
|
}
|
|
|
Instr Assembler::ImmTestBranch(int imm14) {
|
CHECK(is_int14(imm14));
|
return truncate_to_int14(imm14) << ImmTestBranch_offset;
|
}
|
|
|
Instr Assembler::ImmTestBranchBit(unsigned bit_pos) {
|
DCHECK(is_uint6(bit_pos));
|
// Subtract five from the shift offset, as we need bit 5 from bit_pos.
|
unsigned b5 = bit_pos << (ImmTestBranchBit5_offset - 5);
|
unsigned b40 = bit_pos << ImmTestBranchBit40_offset;
|
b5 &= ImmTestBranchBit5_mask;
|
b40 &= ImmTestBranchBit40_mask;
|
return b5 | b40;
|
}
|
|
|
Instr Assembler::SF(Register rd) {
|
return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits;
|
}
|
|
|
Instr Assembler::ImmAddSub(int imm) {
|
DCHECK(IsImmAddSub(imm));
|
if (is_uint12(imm)) { // No shift required.
|
imm <<= ImmAddSub_offset;
|
} else {
|
imm = ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
|
}
|
return imm;
|
}
|
|
|
Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
|
DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
|
((reg_size == kWRegSizeInBits) && is_uint5(imms)));
|
USE(reg_size);
|
return imms << ImmS_offset;
|
}
|
|
|
Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
|
DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
|
((reg_size == kWRegSizeInBits) && is_uint5(immr)));
|
USE(reg_size);
|
DCHECK(is_uint6(immr));
|
return immr << ImmR_offset;
|
}
|
|
|
Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
|
DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
|
DCHECK(is_uint6(imms));
|
DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
|
USE(reg_size);
|
return imms << ImmSetBits_offset;
|
}
|
|
|
Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
|
DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
|
DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
|
((reg_size == kWRegSizeInBits) && is_uint5(immr)));
|
USE(reg_size);
|
return immr << ImmRotate_offset;
|
}
|
|
|
Instr Assembler::ImmLLiteral(int imm19) {
|
CHECK(is_int19(imm19));
|
return truncate_to_int19(imm19) << ImmLLiteral_offset;
|
}
|
|
|
Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
|
DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
|
DCHECK((reg_size == kXRegSizeInBits) || (bitn == 0));
|
USE(reg_size);
|
return bitn << BitN_offset;
|
}
|
|
|
Instr Assembler::ShiftDP(Shift shift) {
|
DCHECK(shift == LSL || shift == LSR || shift == ASR || shift == ROR);
|
return shift << ShiftDP_offset;
|
}
|
|
|
Instr Assembler::ImmDPShift(unsigned amount) {
|
DCHECK(is_uint6(amount));
|
return amount << ImmDPShift_offset;
|
}
|
|
|
Instr Assembler::ExtendMode(Extend extend) {
|
return extend << ExtendMode_offset;
|
}
|
|
|
Instr Assembler::ImmExtendShift(unsigned left_shift) {
|
DCHECK_LE(left_shift, 4);
|
return left_shift << ImmExtendShift_offset;
|
}
|
|
|
Instr Assembler::ImmCondCmp(unsigned imm) {
|
DCHECK(is_uint5(imm));
|
return imm << ImmCondCmp_offset;
|
}
|
|
|
Instr Assembler::Nzcv(StatusFlags nzcv) {
|
return ((nzcv >> Flags_offset) & 0xf) << Nzcv_offset;
|
}
|
|
|
Instr Assembler::ImmLSUnsigned(int imm12) {
|
DCHECK(is_uint12(imm12));
|
return imm12 << ImmLSUnsigned_offset;
|
}
|
|
|
Instr Assembler::ImmLS(int imm9) {
|
DCHECK(is_int9(imm9));
|
return truncate_to_int9(imm9) << ImmLS_offset;
|
}
|
|
Instr Assembler::ImmLSPair(int imm7, unsigned size) {
|
DCHECK_EQ((imm7 >> size) << size, imm7);
|
int scaled_imm7 = imm7 >> size;
|
DCHECK(is_int7(scaled_imm7));
|
return truncate_to_int7(scaled_imm7) << ImmLSPair_offset;
|
}
|
|
|
Instr Assembler::ImmShiftLS(unsigned shift_amount) {
|
DCHECK(is_uint1(shift_amount));
|
return shift_amount << ImmShiftLS_offset;
|
}
|
|
|
Instr Assembler::ImmException(int imm16) {
|
DCHECK(is_uint16(imm16));
|
return imm16 << ImmException_offset;
|
}
|
|
|
Instr Assembler::ImmSystemRegister(int imm15) {
|
DCHECK(is_uint15(imm15));
|
return imm15 << ImmSystemRegister_offset;
|
}
|
|
|
Instr Assembler::ImmHint(int imm7) {
|
DCHECK(is_uint7(imm7));
|
return imm7 << ImmHint_offset;
|
}
|
|
|
Instr Assembler::ImmBarrierDomain(int imm2) {
|
DCHECK(is_uint2(imm2));
|
return imm2 << ImmBarrierDomain_offset;
|
}
|
|
|
Instr Assembler::ImmBarrierType(int imm2) {
|
DCHECK(is_uint2(imm2));
|
return imm2 << ImmBarrierType_offset;
|
}
|
|
unsigned Assembler::CalcLSDataSize(LoadStoreOp op) {
|
DCHECK((LSSize_offset + LSSize_width) == (kInstrSize * 8));
|
unsigned size = static_cast<Instr>(op >> LSSize_offset);
|
if ((op & LSVector_mask) != 0) {
|
// Vector register memory operations encode the access size in the "size"
|
// and "opc" fields.
|
if ((size == 0) && ((op & LSOpc_mask) >> LSOpc_offset) >= 2) {
|
size = kQRegSizeLog2;
|
}
|
}
|
return size;
|
}
|
|
|
Instr Assembler::ImmMoveWide(int imm) {
|
DCHECK(is_uint16(imm));
|
return imm << ImmMoveWide_offset;
|
}
|
|
|
Instr Assembler::ShiftMoveWide(int shift) {
|
DCHECK(is_uint2(shift));
|
return shift << ShiftMoveWide_offset;
|
}
|
|
Instr Assembler::FPType(VRegister fd) { return fd.Is64Bits() ? FP64 : FP32; }
|
|
Instr Assembler::FPScale(unsigned scale) {
|
DCHECK(is_uint6(scale));
|
return scale << FPScale_offset;
|
}
|
|
|
const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const {
|
return reg.Is64Bits() ? xzr : wzr;
|
}
|
|
|
inline void Assembler::CheckBufferSpace() {
|
DCHECK(pc_ < (buffer_ + buffer_size_));
|
if (buffer_space() < kGap) {
|
GrowBuffer();
|
}
|
}
|
|
|
inline void Assembler::CheckBuffer() {
|
CheckBufferSpace();
|
if (pc_offset() >= next_veneer_pool_check_) {
|
CheckVeneerPool(false, true);
|
}
|
if (pc_offset() >= next_constant_pool_check_) {
|
CheckConstPool(false, true);
|
}
|
}
|
|
} // namespace internal
|
} // namespace v8
|
|
#endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_
|
