// Copyright 2018 The Gemmlowp Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// output_msa.h: optimized MSA specializations of the templates in output.h.
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#ifndef GEMMLOWP_INTERNAL_OUTPUT_MSA_H_
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#define GEMMLOWP_INTERNAL_OUTPUT_MSA_H_
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#include "output.h"
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#include <msa.h>
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namespace gemmlowp {
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToUint8,
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RegBufferInt32<4>> {
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typedef RegBufferInt32<4> InputType;
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typedef RegBufferUint8<4> OutputType;
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typedef OutputStageSaturatingCastToUint8 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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// Signed saturate each 32-bit element to 9 bits
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// (this takes full care of non-negative elements).
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v4i32 tmp = __builtin_msa_sat_s_w(input.reg[0], 8);
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// Pack every 32-bit element into 16 bits.
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tmp = reinterpret_cast<v4i32>(__builtin_msa_pckev_h(
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reinterpret_cast<v8i16>(tmp), reinterpret_cast<v8i16>(tmp)));
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// Detect negative elements with arithmetic shift right (we
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// get a 16-bit mask of all zeroes or all ones for every element).
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v8i16 signs = __builtin_msa_srai_h(reinterpret_cast<v8i16>(tmp), 15);
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// Zero out negative elements.
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signs = reinterpret_cast<v8i16>(__builtin_msa_bseli_b(
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reinterpret_cast<v16u8>(signs), reinterpret_cast<v16u8>(tmp), 0));
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// Pack every element into 8 bits.
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tmp = reinterpret_cast<v4i32>(__builtin_msa_pckev_b(
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reinterpret_cast<v16i8>(signs), reinterpret_cast<v16i8>(signs)));
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// Return 4 uint8_t elements as uint32_t.
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output.reg[0] = __builtin_msa_copy_s_w(tmp, 0);
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return output;
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}
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};
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToUint8,
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RegBufferInt32<8>> {
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typedef RegBufferInt32<8> InputType;
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typedef RegBufferUint8<8> OutputType;
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typedef OutputStageSaturatingCastToUint8 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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// Signed saturate each 32-bit element to 9 bits
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// (this takes full care of non-negative elements).
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v4i32 tmp_lo = __builtin_msa_sat_s_w(input.reg[0], 8);
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v4i32 tmp_hi = __builtin_msa_sat_s_w(input.reg[1], 8);
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// Pack every 32-bit element into 16 bits,
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// combining all 8 elements into one vector.
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tmp_lo = reinterpret_cast<v4i32>(__builtin_msa_pckev_h(
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reinterpret_cast<v8i16>(tmp_hi), reinterpret_cast<v8i16>(tmp_lo)));
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// Detect negative elements with arithmetic shift right (we
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// get a 16-bit mask of all zeroes or all ones for every element).
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v8i16 signs = __builtin_msa_srai_h(reinterpret_cast<v8i16>(tmp_lo), 15);
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// Zero out negative elements.
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signs = reinterpret_cast<v8i16>(__builtin_msa_bseli_b(
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reinterpret_cast<v16u8>(signs), reinterpret_cast<v16u8>(tmp_lo), 0));
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// Pack every element into 8 bits.
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tmp_lo = reinterpret_cast<v4i32>(__builtin_msa_pckev_b(
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reinterpret_cast<v16i8>(signs), reinterpret_cast<v16i8>(signs)));
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// Return 8 uint8_t elements as 2 uint32_t's.
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output.reg[0] = __builtin_msa_copy_s_w(tmp_lo, 0);
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output.reg[1] = __builtin_msa_copy_s_w(tmp_lo, 1);
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return output;
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}
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};
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#define GEMMLOWP_MIPS_SAT_U8_16(out, in0, in1, in2, in3) \
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{ \
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v4i32 tmp0 = __builtin_msa_sat_s_w(in0, 8); \
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v4i32 tmp1 = __builtin_msa_sat_s_w(in1, 8); \
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v4i32 tmp2 = __builtin_msa_sat_s_w(in2, 8); \
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v4i32 tmp3 = __builtin_msa_sat_s_w(in3, 8); \
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tmp0 = reinterpret_cast<v4i32>(__builtin_msa_pckev_h( \
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reinterpret_cast<v8i16>(tmp1), reinterpret_cast<v8i16>(tmp0))); \
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tmp2 = reinterpret_cast<v4i32>(__builtin_msa_pckev_h( \
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reinterpret_cast<v8i16>(tmp3), reinterpret_cast<v8i16>(tmp2))); \
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v8i16 signs0 = __builtin_msa_srai_h(reinterpret_cast<v8i16>(tmp0), 15); \
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v8i16 signs1 = __builtin_msa_srai_h(reinterpret_cast<v8i16>(tmp2), 15); \
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signs0 = reinterpret_cast<v8i16>(__builtin_msa_bseli_b( \
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reinterpret_cast<v16u8>(signs0), reinterpret_cast<v16u8>(tmp0), 0)); \
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signs1 = reinterpret_cast<v8i16>(__builtin_msa_bseli_b( \
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reinterpret_cast<v16u8>(signs1), reinterpret_cast<v16u8>(tmp2), 0)); \
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signs0 = reinterpret_cast<v8i16>(__builtin_msa_pckev_b( \
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reinterpret_cast<v16i8>(signs1), reinterpret_cast<v16i8>(signs0))); \
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out = reinterpret_cast<v16i8>(signs0); \
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}
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToUint8,
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RegBufferInt32<16>> {
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typedef RegBufferInt32<16> InputType;
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typedef RegBufferUint8<16> OutputType;
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typedef OutputStageSaturatingCastToUint8 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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GEMMLOWP_MIPS_SAT_U8_16(output.reg[0], input.reg[0], input.reg[1],
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input.reg[2], input.reg[3]);
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return output;
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}
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};
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToUint8,
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RegBufferInt32<32>> {
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typedef RegBufferInt32<32> InputType;
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typedef RegBufferUint8<32> OutputType;
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typedef OutputStageSaturatingCastToUint8 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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GEMMLOWP_MIPS_SAT_U8_16(output.reg[0], input.reg[0], input.reg[1],
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input.reg[2], input.reg[3]);
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GEMMLOWP_MIPS_SAT_U8_16(output.reg[1], input.reg[4], input.reg[5],
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input.reg[6], input.reg[7]);
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return output;
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}
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};
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#undef GEMMLOWP_MIPS_SAT_U8_16
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToInt16,
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RegBufferInt32<4>> {
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typedef RegBufferInt32<4> InputType;
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typedef RegBufferInt16<4> OutputType;
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typedef OutputStageSaturatingCastToInt16 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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// Signed saturate each 32-bit element to 16 bits.
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v8i16 tmp = reinterpret_cast<v8i16>(__builtin_msa_sat_s_w(
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input.reg[0], 15));
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output.reg[0] = __builtin_msa_copy_s_h(tmp, 0);
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output.reg[1] = __builtin_msa_copy_s_h(tmp, 2);
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output.reg[2] = __builtin_msa_copy_s_h(tmp, 4);
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output.reg[3] = __builtin_msa_copy_s_h(tmp, 6);
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return output;
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}
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};
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#define GEMMLOWP_MIPS_SAT_I16_8(out, in0, in1) \
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{ \
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v4i32 tmp0 = __builtin_msa_sat_s_w(in0, 15); \
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v4i32 tmp1 = __builtin_msa_sat_s_w(in1, 15); \
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out = __builtin_msa_pckev_h( \
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reinterpret_cast<v8i16>(tmp1), reinterpret_cast<v8i16>(tmp0)); \
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}
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToInt16,
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RegBufferInt32<8>> {
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typedef RegBufferInt32<8> InputType;
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typedef RegBufferInt16<8> OutputType;
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typedef OutputStageSaturatingCastToInt16 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[0], input.reg[0], input.reg[1]);
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return output;
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}
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};
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToInt16,
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RegBufferInt32<16>> {
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typedef RegBufferInt32<16> InputType;
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typedef RegBufferInt16<16> OutputType;
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typedef OutputStageSaturatingCastToInt16 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[0], input.reg[0], input.reg[1]);
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[1], input.reg[2], input.reg[3]);
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return output;
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}
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};
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template <>
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struct OutputStageEvalBufferImpl<OutputStageSaturatingCastToInt16,
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RegBufferInt32<32>> {
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typedef RegBufferInt32<32> InputType;
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typedef RegBufferInt16<32> OutputType;
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typedef OutputStageSaturatingCastToInt16 OutputStage;
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OutputStageEvalBufferImpl(const OutputStage&) {}
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OutputType Eval(InputType input) const {
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OutputType output;
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[0], input.reg[0], input.reg[1]);
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[1], input.reg[2], input.reg[3]);
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[2], input.reg[4], input.reg[5]);
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GEMMLOWP_MIPS_SAT_I16_8(output.reg[3], input.reg[6], input.reg[7]);
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return output;
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}
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};
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#undef GEMMLOWP_MIPS_SAT_I16_8
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt32<4, 1>, DstType> {
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static void Run(const RegBlockInt32<4, 1>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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StoreInt32x4(dst->data(row, col), src.buf.reg[0]);
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} else {
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*dst->data(row + 0, col) = GetLane<0>(src.buf.reg[0]);
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*dst->data(row + 1, col) = GetLane<1>(src.buf.reg[0]);
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*dst->data(row + 2, col) = GetLane<2>(src.buf.reg[0]);
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*dst->data(row + 3, col) = GetLane<3>(src.buf.reg[0]);
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}
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt32<8, 1>, DstType> {
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static void Run(const RegBlockInt32<8, 1>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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StoreInt32x4(dst->data(row, col), src.buf.reg[0]);
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StoreInt32x4(dst->data(row + 4, col), src.buf.reg[1]);
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} else {
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*dst->data(row + 0, col) = GetLane<0>(src.buf.reg[0]);
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*dst->data(row + 1, col) = GetLane<1>(src.buf.reg[0]);
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*dst->data(row + 2, col) = GetLane<2>(src.buf.reg[0]);
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*dst->data(row + 3, col) = GetLane<3>(src.buf.reg[0]);
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*dst->data(row + 4, col) = GetLane<0>(src.buf.reg[1]);
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*dst->data(row + 5, col) = GetLane<1>(src.buf.reg[1]);
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*dst->data(row + 6, col) = GetLane<2>(src.buf.reg[1]);
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*dst->data(row + 7, col) = GetLane<3>(src.buf.reg[1]);
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}
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt16<4, 1>, DstType> {
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static void Run(const RegBlockInt16<4, 1>& src, DstType* dst, int row,
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int col) {
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*dst->data(row + 0, col) = src.buf.reg[0];
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*dst->data(row + 1, col) = src.buf.reg[1];
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*dst->data(row + 2, col) = src.buf.reg[2];
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*dst->data(row + 3, col) = src.buf.reg[3];
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt16<8, 1>, DstType> {
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static void Run(const RegBlockInt16<8, 1>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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StoreInt16x8(dst->data(row, col), src.buf.reg[0]);
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} else {
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*dst->data(row + 0, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 0);
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*dst->data(row + 1, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 1);
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*dst->data(row + 2, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 2);
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*dst->data(row + 3, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 3);
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*dst->data(row + 4, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 4);
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*dst->data(row + 5, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 5);
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*dst->data(row + 6, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 6);
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*dst->data(row + 7, col) = __builtin_msa_copy_s_h(src.buf.reg[0], 7);
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}
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}
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};
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inline RegBlockInt32<4, 4> Transpose(const RegBlockInt32<4, 4>& src) {
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RegBlockInt32<4, 4> result;
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v4i32 tmp0, tmp1;
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tmp0 = __builtin_msa_ilvr_w(src.buf.reg[1], src.buf.reg[0]);
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tmp1 = __builtin_msa_ilvr_w(src.buf.reg[3], src.buf.reg[2]);
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result.buf.reg[0] = reinterpret_cast<v4i32>(__builtin_msa_ilvr_d(
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reinterpret_cast<v2i64>(tmp1), reinterpret_cast<v2i64>(tmp0)));
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result.buf.reg[1] = reinterpret_cast<v4i32>(__builtin_msa_ilvl_d(
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reinterpret_cast<v2i64>(tmp1), reinterpret_cast<v2i64>(tmp0)));
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tmp0 = __builtin_msa_ilvl_w(src.buf.reg[1], src.buf.reg[0]);
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tmp1 = __builtin_msa_ilvl_w(src.buf.reg[3], src.buf.reg[2]);
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result.buf.reg[2] = reinterpret_cast<v4i32>(__builtin_msa_ilvr_d(
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reinterpret_cast<v2i64>(tmp1), reinterpret_cast<v2i64>(tmp0)));
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result.buf.reg[3] = reinterpret_cast<v4i32>(__builtin_msa_ilvl_d(
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reinterpret_cast<v2i64>(tmp1), reinterpret_cast<v2i64>(tmp0)));
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return result;
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}
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt32<4, 4>, DstType> {
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static void Run(const RegBlockInt32<4, 4>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row, col + i), src.buf.reg[i]);
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}
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} else {
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const auto transpose = Transpose(src);
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row + i, col), transpose.buf.reg[i]);
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}
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}
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt16<4, 4>, DstType> {
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static void Run(const RegBlockInt16<4, 4>& src, DstType* dst, int row,
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int col) {
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std::int16_t buf[16];
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StoreInt16x8(buf + 0, src.buf.reg[0]);
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StoreInt16x8(buf + 8, src.buf.reg[1]);
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for (int i = 0; i < 4; i++) {
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for (int j = 0; j < 4; j++) {
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*dst->data(row + i, col + j) = buf[i + 4 * j];
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}
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}
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt32<8, 4>, DstType> {
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static void Run(const RegBlockInt32<8, 4>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row, col + i), src.buf.reg[2 * i]);
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StoreInt32x4(dst->data(row + 4, col + i), src.buf.reg[2 * i + 1]);
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}
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} else {
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RegBlockInt32<4, 4> top;
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top.buf.reg[0] = src.buf.reg[0];
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top.buf.reg[1] = src.buf.reg[2];
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top.buf.reg[2] = src.buf.reg[4];
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top.buf.reg[3] = src.buf.reg[6];
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const auto transpose_top = Transpose(top);
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row + i, col), transpose_top.buf.reg[i]);
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}
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RegBlockInt32<4, 4> bottom;
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bottom.buf.reg[0] = src.buf.reg[1];
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bottom.buf.reg[1] = src.buf.reg[3];
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bottom.buf.reg[2] = src.buf.reg[5];
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bottom.buf.reg[3] = src.buf.reg[7];
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const auto transpose_bottom = Transpose(bottom);
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row + 4 + i, col), transpose_bottom.buf.reg[i]);
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}
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}
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt16<8, 4>, DstType> {
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static void Run(const RegBlockInt16<8, 4>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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for (int i = 0; i < 4; i++) {
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StoreInt16x8(dst->data(row, col + i), src.buf.reg[i]);
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}
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} else {
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std::int16_t buf[32];
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StoreInt16x8(buf + 0, src.buf.reg[0]);
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StoreInt16x8(buf + 8, src.buf.reg[1]);
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StoreInt16x8(buf + 16, src.buf.reg[2]);
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StoreInt16x8(buf + 24, src.buf.reg[3]);
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for (int i = 0; i < 8; i++) {
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for (int j = 0; j < 4; j++) {
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*dst->data(row + i, col + j) = buf[i + 8 * j];
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}
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}
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}
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}
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};
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template <typename DstType>
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struct StoreFinalOutputImpl<RegBlockInt32<8, 8>, DstType> {
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static void Run(const RegBlockInt32<8, 8>& src, DstType* dst, int row,
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int col) {
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if (DstType::kOrder == MapOrder::ColMajor) {
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for (int i = 0; i < 8; i++) {
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StoreInt32x4(dst->data(row, col + i), src.buf.reg[2 * i]);
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StoreInt32x4(dst->data(row + 4, col + i), src.buf.reg[2 * i + 1]);
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}
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} else {
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RegBlockInt32<4, 4> top_left;
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top_left.buf.reg[0] = src.buf.reg[0];
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top_left.buf.reg[1] = src.buf.reg[2];
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top_left.buf.reg[2] = src.buf.reg[4];
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top_left.buf.reg[3] = src.buf.reg[6];
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const auto transpose_top_left = Transpose(top_left);
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row + i, col), transpose_top_left.buf.reg[i]);
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}
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RegBlockInt32<4, 4> bottom_left;
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bottom_left.buf.reg[0] = src.buf.reg[1];
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bottom_left.buf.reg[1] = src.buf.reg[3];
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bottom_left.buf.reg[2] = src.buf.reg[5];
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bottom_left.buf.reg[3] = src.buf.reg[7];
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const auto transpose_bottom_left = Transpose(bottom_left);
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row + 4 + i, col),
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transpose_bottom_left.buf.reg[i]);
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}
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RegBlockInt32<4, 4> top_right;
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top_right.buf.reg[0] = src.buf.reg[8];
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top_right.buf.reg[1] = src.buf.reg[10];
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top_right.buf.reg[2] = src.buf.reg[12];
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top_right.buf.reg[3] = src.buf.reg[14];
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const auto transpose_top_right = Transpose(top_right);
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for (int i = 0; i < 4; i++) {
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StoreInt32x4(dst->data(row + i, col + 4),
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transpose_top_right.buf.reg[i]);
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}
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RegBlockInt32<4, 4> bottom_right;
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bottom_right.buf.reg[0] = src.buf.reg[9];
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bottom_right.buf.reg[1] = src.buf.reg[11];
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bottom_right.buf.reg[2] = src.buf.reg[13];
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bottom_right.buf.reg[3] = src.buf.reg[15];
|
const auto transpose_bottom_right = Transpose(bottom_right);
|
for (int i = 0; i < 4; i++) {
|
StoreInt32x4(dst->data(row + 4 + i, col + 4),
|
transpose_bottom_right.buf.reg[i]);
|
}
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockInt16<8, 8>, DstType> {
|
static void Run(const RegBlockInt16<8, 8>& src, DstType* dst, int row,
|
int col) {
|
if (DstType::kOrder == MapOrder::ColMajor) {
|
for (int i = 0; i < 8; i++) {
|
StoreInt16x8(dst->data(row, col + i), src.buf.reg[i]);
|
}
|
} else {
|
// top-left 4x4
|
v4i32 t0 = reinterpret_cast<v4i32>(__builtin_msa_ilvr_h(src.buf.reg[1],
|
src.buf.reg[0]));
|
v4i32 t1 = reinterpret_cast<v4i32>(__builtin_msa_ilvr_h(src.buf.reg[3],
|
src.buf.reg[2]));
|
v2i64 u0 = reinterpret_cast<v2i64>(__builtin_msa_ilvr_w(t1, t0));
|
v2i64 u1 = reinterpret_cast<v2i64>(__builtin_msa_ilvl_w(t1, t0));
|
// top-right 4x4
|
v4i32 t2 = reinterpret_cast<v4i32>(__builtin_msa_ilvr_h(src.buf.reg[5],
|
src.buf.reg[4]));
|
v4i32 t3 = reinterpret_cast<v4i32>(__builtin_msa_ilvr_h(src.buf.reg[7],
|
src.buf.reg[6]));
|
v2i64 u2 = reinterpret_cast<v2i64>(__builtin_msa_ilvr_w(t3, t2));
|
v2i64 u3 = reinterpret_cast<v2i64>(__builtin_msa_ilvl_w(t3, t2));
|
// bottom-left 4x4
|
v4i32 t4 = reinterpret_cast<v4i32>(__builtin_msa_ilvl_h(src.buf.reg[1],
|
src.buf.reg[0]));
|
v4i32 t5 = reinterpret_cast<v4i32>(__builtin_msa_ilvl_h(src.buf.reg[3],
|
src.buf.reg[2]));
|
v2i64 u4 = reinterpret_cast<v2i64>(__builtin_msa_ilvr_w(t5, t4));
|
v2i64 u5 = reinterpret_cast<v2i64>(__builtin_msa_ilvl_w(t5, t4));
|
// bottom-right 4x4
|
v4i32 t6 = reinterpret_cast<v4i32>(__builtin_msa_ilvl_h(src.buf.reg[5],
|
src.buf.reg[4]));
|
v4i32 t7 = reinterpret_cast<v4i32>(__builtin_msa_ilvl_h(src.buf.reg[7],
|
src.buf.reg[6]));
|
v2i64 u6 = reinterpret_cast<v2i64>(__builtin_msa_ilvr_w(t7, t6));
|
v2i64 u7 = reinterpret_cast<v2i64>(__builtin_msa_ilvl_w(t7, t6));
|
|
StoreInt16x8(dst->data(row + 0, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvr_d(u2, u0)));
|
StoreInt16x8(dst->data(row + 1, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvl_d(u2, u0)));
|
StoreInt16x8(dst->data(row + 2, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvr_d(u3, u1)));
|
StoreInt16x8(dst->data(row + 3, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvl_d(u3, u1)));
|
StoreInt16x8(dst->data(row + 4, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvr_d(u6, u4)));
|
StoreInt16x8(dst->data(row + 5, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvl_d(u6, u4)));
|
StoreInt16x8(dst->data(row + 6, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvr_d(u7, u5)));
|
StoreInt16x8(dst->data(row + 7, col), reinterpret_cast<v8i16>(
|
__builtin_msa_ilvl_d(u7, u5)));
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockInt32<1, 4>, DstType> {
|
static void Run(const RegBlockInt32<1, 4>& src, DstType* dst, int row,
|
int col) {
|
if (DstType::kOrder == MapOrder::ColMajor) {
|
*dst->data(row, col + 0) = GetLane<0>(src.buf.reg[0]);
|
*dst->data(row, col + 1) = GetLane<1>(src.buf.reg[0]);
|
*dst->data(row, col + 2) = GetLane<2>(src.buf.reg[0]);
|
*dst->data(row, col + 3) = GetLane<3>(src.buf.reg[0]);
|
} else {
|
StoreInt32x4(dst->data(row, col), src.buf.reg[0]);
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockUint8<4, 1>, DstType> {
|
static void Run(const RegBlockUint8<4, 1>& src, DstType* dst, int row,
|
int col) {
|
const std::uint32_t src_reg = src.buf.reg[0];
|
for (int i = 0; i < 4; i++) {
|
*dst->data(row + i, col) = (src_reg >> (8 * i));
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockUint8<8, 1>, DstType> {
|
static void Run(const RegBlockUint8<8, 1>& src, DstType* dst, int row,
|
int col) {
|
for (int i = 0; i < 4; i++) {
|
*dst->data(row + i, col) = (src.buf.reg[0] >> (8 * i));
|
}
|
for (int i = 0; i < 4; i++) {
|
*dst->data(row + 4 + i, col) = (src.buf.reg[1] >> (8 * i));
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockUint8<1, 4>, DstType> {
|
static void Run(const RegBlockUint8<1, 4>& src, DstType* dst, int row,
|
int col) {
|
for (int i = 0; i < 4; i++) {
|
*dst->data(row, col + i) = (src.buf.reg[0] >> (8 * i));
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockUint8<4, 4>, DstType> {
|
static void Run(const RegBlockUint8<4, 4>& src, DstType* dst, int row,
|
int col) {
|
std::uint8_t buf[16];
|
StoreUint8x16(buf, src.buf.reg[0]);
|
for (int c = 0; c < 4; c++) {
|
for (int r = 0; r < 4; r++) {
|
*dst->data(row + r, col + c) = buf[r + 4 * c];
|
}
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockUint8<8, 4>, DstType> {
|
static void Run(const RegBlockUint8<8, 4>& src, DstType* dst, int row,
|
int col) {
|
std::uint8_t buf[32];
|
StoreUint8x16(buf, src.buf.reg[0]);
|
StoreUint8x16(buf + 16, src.buf.reg[1]);
|
for (int c = 0; c < 4; c++) {
|
for (int r = 0; r < 8; r++) {
|
*dst->data(row + r, col + c) = buf[r + 8 * c];
|
}
|
}
|
}
|
};
|
|
template <typename DstType>
|
struct StoreFinalOutputImpl<RegBlockUint8<8, 8>, DstType> {
|
static void Run(const RegBlockUint8<8, 8>& src, DstType* dst, int row,
|
int col) {
|
std::uint8_t buf[64];
|
StoreUint8x16(buf, src.buf.reg[0]);
|
StoreUint8x16(buf + 16, src.buf.reg[1]);
|
StoreUint8x16(buf + 32, src.buf.reg[2]);
|
StoreUint8x16(buf + 48, src.buf.reg[3]);
|
for (int c = 0; c < 8; c++) {
|
for (int r = 0; r < 8; r++) {
|
*dst->data(row + r, col + c) = buf[r + 8 * c];
|
}
|
}
|
}
|
};
|
|
} // namespace gemmlowp
|
|
#endif // GEMMLOWP_INTERNAL_OUTPUT_MSA_H_
|
