/*
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* Error Corrected Code Controller (ECC) - System peripherals regsters.
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* Based on AT91SAM9260 datasheet revision B.
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 - 2012 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef ATMEL_NAND_ECC_H
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#define ATMEL_NAND_ECC_H
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#define ATMEL_ECC_CR 0x00 /* Control register */
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#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
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#define ATMEL_ECC_MR 0x04 /* Mode register */
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#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
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#define ATMEL_ECC_PAGESIZE_528 (0)
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#define ATMEL_ECC_PAGESIZE_1056 (1)
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#define ATMEL_ECC_PAGESIZE_2112 (2)
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#define ATMEL_ECC_PAGESIZE_4224 (3)
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#define ATMEL_ECC_SR 0x08 /* Status register */
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#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
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#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
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#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
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#define ATMEL_ECC_PR 0x0c /* Parity register */
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#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
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#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
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#define ATMEL_ECC_NPR 0x10 /* NParity register */
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#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
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/* PMECC Register Definitions */
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#define ATMEL_PMECC_CFG 0x000 /* Configuration Register */
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#define PMECC_CFG_BCH_ERR2 (0 << 0)
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#define PMECC_CFG_BCH_ERR4 (1 << 0)
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#define PMECC_CFG_BCH_ERR8 (2 << 0)
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#define PMECC_CFG_BCH_ERR12 (3 << 0)
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#define PMECC_CFG_BCH_ERR24 (4 << 0)
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#define PMECC_CFG_BCH_ERR32 (5 << 0)
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#define PMECC_CFG_SECTOR512 (0 << 4)
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#define PMECC_CFG_SECTOR1024 (1 << 4)
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#define PMECC_CFG_PAGE_1SECTOR (0 << 8)
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#define PMECC_CFG_PAGE_2SECTORS (1 << 8)
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#define PMECC_CFG_PAGE_4SECTORS (2 << 8)
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#define PMECC_CFG_PAGE_8SECTORS (3 << 8)
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#define PMECC_CFG_READ_OP (0 << 12)
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#define PMECC_CFG_WRITE_OP (1 << 12)
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#define PMECC_CFG_SPARE_ENABLE (1 << 16)
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#define PMECC_CFG_SPARE_DISABLE (0 << 16)
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#define PMECC_CFG_AUTO_ENABLE (1 << 20)
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#define PMECC_CFG_AUTO_DISABLE (0 << 20)
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#define ATMEL_PMECC_SAREA 0x004 /* Spare area size */
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#define ATMEL_PMECC_SADDR 0x008 /* PMECC starting address */
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#define ATMEL_PMECC_EADDR 0x00c /* PMECC ending address */
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#define ATMEL_PMECC_CLK 0x010 /* PMECC clock control */
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#define PMECC_CLK_133MHZ (2 << 0)
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#define ATMEL_PMECC_CTRL 0x014 /* PMECC control register */
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#define PMECC_CTRL_RST (1 << 0)
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#define PMECC_CTRL_DATA (1 << 1)
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#define PMECC_CTRL_USER (1 << 2)
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#define PMECC_CTRL_ENABLE (1 << 4)
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#define PMECC_CTRL_DISABLE (1 << 5)
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#define ATMEL_PMECC_SR 0x018 /* PMECC status register */
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#define PMECC_SR_BUSY (1 << 0)
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#define PMECC_SR_ENABLE (1 << 4)
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#define ATMEL_PMECC_IER 0x01c /* PMECC interrupt enable */
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#define PMECC_IER_ENABLE (1 << 0)
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#define ATMEL_PMECC_IDR 0x020 /* PMECC interrupt disable */
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#define PMECC_IER_DISABLE (1 << 0)
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#define ATMEL_PMECC_IMR 0x024 /* PMECC interrupt mask */
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#define PMECC_IER_MASK (1 << 0)
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#define ATMEL_PMECC_ISR 0x028 /* PMECC interrupt status */
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#define ATMEL_PMECC_ECCx 0x040 /* PMECC ECC x */
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#define ATMEL_PMECC_REMx 0x240 /* PMECC REM x */
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/* PMERRLOC Register Definitions */
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#define ATMEL_PMERRLOC_ELCFG 0x000 /* Error location config */
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#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
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#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
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#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
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#define ATMEL_PMERRLOC_ELPRIM 0x004 /* Error location primitive */
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#define ATMEL_PMERRLOC_ELEN 0x008 /* Error location enable */
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#define ATMEL_PMERRLOC_ELDIS 0x00c /* Error location disable */
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#define PMERRLOC_DISABLE (1 << 0)
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#define ATMEL_PMERRLOC_ELSR 0x010 /* Error location status */
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#define PMERRLOC_ELSR_BUSY (1 << 0)
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#define ATMEL_PMERRLOC_ELIER 0x014 /* Error location int enable */
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#define ATMEL_PMERRLOC_ELIDR 0x018 /* Error location int disable */
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#define ATMEL_PMERRLOC_ELIMR 0x01c /* Error location int mask */
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#define ATMEL_PMERRLOC_ELISR 0x020 /* Error location int status */
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#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
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#define PMERRLOC_CALC_DONE (1 << 0)
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#define ATMEL_PMERRLOC_SIGMAx 0x028 /* Error location SIGMA x */
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/*
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* The ATMEL_PMERRLOC_ELx register location depends from the number of
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* bits corrected by the PMECC controller. Do not use it.
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*/
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/* Register access macros for PMECC */
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#define pmecc_readl_relaxed(addr, reg) \
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readl_relaxed((addr) + ATMEL_PMECC_##reg)
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#define pmecc_writel(addr, reg, value) \
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writel((value), (addr) + ATMEL_PMECC_##reg)
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#define pmecc_readb_ecc_relaxed(addr, sector, n) \
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readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
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#define pmecc_readl_rem_relaxed(addr, sector, n) \
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readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
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#define pmerrloc_readl_relaxed(addr, reg) \
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readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
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#define pmerrloc_writel(addr, reg, value) \
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writel((value), (addr) + ATMEL_PMERRLOC_##reg)
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#define pmerrloc_writel_sigma_relaxed(addr, n, value) \
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writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
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#define pmerrloc_readl_sigma_relaxed(addr, n) \
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readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
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#define pmerrloc_readl_el_relaxed(addr, n) \
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readl_relaxed((addr) + ((n) * 4))
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/* Galois field dimension */
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#define PMECC_GF_DIMENSION_13 13
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#define PMECC_GF_DIMENSION_14 14
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/* Primitive Polynomial used by PMECC */
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#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
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#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
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#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000
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#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000
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/* Time out value for reading PMECC status register */
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#define PMECC_MAX_TIMEOUT_MS 100
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/* Reserved bytes in oob area */
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#define PMECC_OOB_RESERVED_BYTES 2
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#endif
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