/*
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* Allwinner SoCs tv driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "drv_tv.h"
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#include "de_tvec.h"
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#include <linux/sunxi-sid.h>
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static void __iomem *tve_reg_base[TVE_DEVICE_NUM];
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static void __iomem *sid_reg_base;
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static s32 tve_low_dac_auto_cali(u32 sel, u32 *cali);
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s32 tve_low_set_reg_base(u32 sel, void __iomem *address)
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{
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if (sel < TVE_DEVICE_NUM)
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tve_reg_base[sel] = address;
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return 0;
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}
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s32 tve_low_set_top_reg_base(void __iomem *address)
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{
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return 0;
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}
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s32 tve_low_set_sid_base(void __iomem *address)
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{
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sid_reg_base = address;
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return 0;
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}
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s32 tve_low_init(u32 sel, u32 *dac_no, u32 *cali, s32 *offset,
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u32 *dac_type, u32 num)
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{
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s32 val = (*cali) ? (*cali) : 0x285;
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val += *offset;
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TVE_WUINT32(sel, TVE_304, val << 16);
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TVE_WUINT32(sel, TVE_30C, 0x00101110);
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TVE_WUINT32(sel, TVE_008, 0x433e12b1);
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TVE_WUINT32(sel, TVE_000, 0x80000000);
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return 0;
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}
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s32 tve_low_exit(u32 sel)
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{
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return 0;
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}
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s32 tve_low_dac_enable(u32 sel)
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{
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TVE_SET_BIT(sel, TVE_008, 0x1 << 0);
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return 0;
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}
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s32 tve_low_dac_disable(u32 sel)
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{
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TVE_CLR_BIT(sel, TVE_008, 0x1 << 0);
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return 0;
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}
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s32 tve_low_open(u32 sel)
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{
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TVE_CLR_BIT(sel, TVE_000, 0x1 << 31);
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TVE_SET_BIT(sel, TVE_000, 0x1 << 0);
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return 0;
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}
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s32 tve_low_close(u32 sel)
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{
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TVE_CLR_BIT(sel, TVE_000, 0x1 << 0);
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TVE_SET_BIT(sel, TVE_000, 0x1 << 31);
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return 0;
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}
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s32 tve_low_set_tv_mode(u32 sel, enum disp_tv_mode mode, u32 *cali)
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{
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tve_low_dac_auto_cali(sel, cali);
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if (mode == DISP_TV_MOD_NTSC) {
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TVE_WUINT32(sel, TVE_000, 0x00000300);
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TVE_WUINT32(sel, TVE_004, 0x07070000);
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TVE_WUINT32(sel, TVE_00C, 0x30001400);
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TVE_WUINT32(sel, TVE_010, 0x21F07C1F);
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TVE_WUINT32(sel, TVE_014, 0x00760020);
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TVE_WUINT32(sel, TVE_018, 0x00000016);
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TVE_WUINT32(sel, TVE_01C, 0x0016020D);
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TVE_WUINT32(sel, TVE_020, 0x00F0011A);
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TVE_WUINT32(sel, TVE_100, 0x00000001);
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TVE_WUINT32(sel, TVE_104, 0x00000000);
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TVE_WUINT32(sel, TVE_108, 0x00000002);
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TVE_WUINT32(sel, TVE_10C, 0x0000004F);
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TVE_WUINT32(sel, TVE_110, 0x00000000);
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TVE_WUINT32(sel, TVE_114, 0x0016447E);
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TVE_WUINT32(sel, TVE_118, 0x0000A0A0);
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TVE_WUINT32(sel, TVE_11C, 0x001000F0);
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TVE_WUINT32(sel, TVE_120, 0x01E80320);
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TVE_WUINT32(sel, TVE_124, 0x000005A0);
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TVE_WUINT32(sel, TVE_128, 0x00010000);
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TVE_WUINT32(sel, TVE_12C, 0x00000101);
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TVE_WUINT32(sel, TVE_130, 0x20050368);
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TVE_WUINT32(sel, TVE_134, 0x00000000);
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TVE_WUINT32(sel, TVE_138, 0x00000000);
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TVE_WUINT32(sel, TVE_13C, 0x00000000);
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} else {
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TVE_WUINT32(sel, TVE_000, 0x00000300);
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TVE_WUINT32(sel, TVE_004, 0x07070001);
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TVE_WUINT32(sel, TVE_00C, 0x30001400);
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TVE_WUINT32(sel, TVE_010, 0x2A098ACB);
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TVE_WUINT32(sel, TVE_014, 0x008A0018);
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TVE_WUINT32(sel, TVE_018, 0x00000016);
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TVE_WUINT32(sel, TVE_01C, 0x00160271);
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TVE_WUINT32(sel, TVE_020, 0x00FC00FC);
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TVE_WUINT32(sel, TVE_100, 0x00000000);
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TVE_WUINT32(sel, TVE_104, 0x00000001);
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TVE_WUINT32(sel, TVE_108, 0x00000005);
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TVE_WUINT32(sel, TVE_10C, 0x00002929);
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TVE_WUINT32(sel, TVE_110, 0x00000000);
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TVE_WUINT32(sel, TVE_114, 0x0016447E);
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TVE_WUINT32(sel, TVE_118, 0x0000A8A8);
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TVE_WUINT32(sel, TVE_11C, 0x001000FC);
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TVE_WUINT32(sel, TVE_120, 0x01E80320);
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TVE_WUINT32(sel, TVE_124, 0x000005A0);
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TVE_WUINT32(sel, TVE_128, 0x00010000);
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TVE_WUINT32(sel, TVE_12C, 0x00000101);
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TVE_WUINT32(sel, TVE_130, 0x2005000A);
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TVE_WUINT32(sel, TVE_134, 0x00000000);
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TVE_WUINT32(sel, TVE_138, 0x00000000);
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TVE_WUINT32(sel, TVE_13C, 0x00000000);
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TVE_WUINT32(sel, TVE_3A0, 0x00030001);
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}
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return 0;
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}
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/* 0:unconnected; 1:connected; 3:short to ground */
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s32 tve_low_get_dac_status(u32 sel)
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{
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u32 readval;
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readval = TVE_RUINT32(sel, TVE_038);
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return readval & 0x3;
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}
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s32 tve_low_dac_autocheck_enable(u32 sel)
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{
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TVE_WUINT32(sel, TVE_0F8, 0x00000280);
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/* 20ms x 10 */
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TVE_WUINT32(sel, TVE_0FC, 0x028F00FF);
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/* 1.0v refer for 0.71v/1.43v detect */
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TVE_WUINT32(sel, TVE_03C, 0x00000009);
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/* detect enable */
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TVE_WUINT32(sel, TVE_030, 0x00000001);
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return 0;
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}
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s32 tve_low_dac_autocheck_disable(u32 sel)
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{
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TVE_WUINT32(sel, TVE_030, 0x0);
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TVE_WUINT32(sel, TVE_0F8, 0x0);
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return 0;
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}
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static s32 tve_low_dac_auto_cali(u32 sel, u32 *cali)
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{
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u32 dac_err_reg[10];
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s32 dac_err_val[10];
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u32 cali_err_1[10];
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u32 cali_err_2[10];
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s32 dac_err_auto;
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s32 dac_err_efuse;
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s32 dac_err_opti;
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u32 dac_err_set;
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u32 i;
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TVE_WUINT32(sel, TVE_000, 0x80000300); /* tvclk enable */
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TVE_WUINT32(sel, TVE_030, 0x00000000); /* auto detect disable */
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TVE_WUINT32(sel, TVE_008, 0x433e12b1); /* dac setting */
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TVE_WUINT32(sel, TVE_304, *cali << 16 | 0xc << 8);
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TVE_SET_BIT(sel, TVE_300, 0x1); /* force DAC for cali */
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for (i = 0; i < 3; i++) {
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TVE_SET_BIT(sel, TVE_304, 0x1 << 4);
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mdelay(1);
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TVE_SET_BIT(sel, TVE_304, 0x1 << 0);
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mdelay(1);
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dac_err_reg[i] = (TVE_RUINT32(sel, TVE_308) >> 16) & 0x3ff;
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TVE_CLR_BIT(sel, TVE_304, 0x1 << 0);
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TVE_CLR_BIT(sel, TVE_304, 0x1 << 4);
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mdelay(1);
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if (dac_err_reg[i] & (1 << 9))
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dac_err_val[i] = 0 + (dac_err_reg[i] & 0x1ff);
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else
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dac_err_val[i] = 0 - (dac_err_reg[i] & 0x1ff);
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}
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cali_err_1[0] = abs(dac_err_val[1] - dac_err_val[0]);
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cali_err_1[1] = abs(dac_err_val[2] - dac_err_val[1]);
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cali_err_1[2] = abs(dac_err_val[0] - dac_err_val[2]);
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cali_err_2[0] = cali_err_1[2] + cali_err_1[0];
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cali_err_2[1] = cali_err_1[0] + cali_err_1[1];
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cali_err_2[2] = cali_err_1[1] + cali_err_1[2];
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if (cali_err_2[0] < cali_err_2[1] && cali_err_2[0] < cali_err_2[2])
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dac_err_auto = dac_err_val[0];
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else if (cali_err_2[1] < cali_err_2[0] && cali_err_2[1] < cali_err_2[2])
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dac_err_auto = dac_err_val[1];
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else
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dac_err_auto = dac_err_val[2];
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if (*cali & (1 << 9))
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dac_err_efuse = 0 + (*cali & 0x1ff);
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else
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dac_err_efuse = 0 - (*cali & 0x1ff);
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if (abs(dac_err_auto - dac_err_efuse) < 100)
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dac_err_opti = dac_err_auto;
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else
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dac_err_opti = dac_err_efuse;
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if (dac_err_opti >= 0)
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dac_err_set = (1 << 9) | dac_err_opti;
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else
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dac_err_set = 0 - dac_err_opti;
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TVE_WUINT32(sel, TVE_304, dac_err_set << 16 | 0xc << 8);
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TVE_CLR_BIT(sel, TVE_300, 0x1);
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TVE_WUINT32(sel, TVE_030, 0x1); /* enable plug detect */
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return 0;
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}
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s32 tve_low_enhance(u32 sel, u32 mode)
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{
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if (mode == 0) {
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TVE_CLR_BIT(sel, TVE_000, 0xf << 10); /* deflick off */
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TVE_SET_BIT(sel, TVE_000, 0x5 << 10); /* deflick is 5 */
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TVE_SET_BIT(sel, TVE_00C, 0x1 << 31); /* lti on */
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TVE_SET_BIT(sel, TVE_00C, 0x1 << 16); /* notch off */
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} else if (mode == 1) {
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TVE_CLR_BIT(sel, TVE_000, 0xf << 10); /* deflick off */
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TVE_SET_BIT(sel, TVE_000, 0x5 << 10); /* deflick is 5 */
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TVE_SET_BIT(sel, TVE_00C, 0x1 << 31); /* lti on */
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TVE_CLR_BIT(sel, TVE_00C, 0x1 << 16); /* notch on */
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} else if (mode == 2) {
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TVE_CLR_BIT(sel, TVE_000, 0xf << 10); /* deflick off */
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TVE_CLR_BIT(sel, TVE_00C, 0x1 << 31); /* lti off */
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TVE_SET_BIT(sel, TVE_00C, 0x1 << 16); /* notch off */
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}
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return 0;
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}
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u32 tve_low_get_sid(u32 index)
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{
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u32 cali_value = 0;
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/* Share register with OEM */
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if (sunxi_efuse_read(EFUSE_OEM_NAME, &cali_value))
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pr_err("get TV%d efuse fail!\n", index);
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else
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return cali_value;
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return 0;
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}
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