/*
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* * Copyright 2000-2009
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* * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* *
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* * SPDX-License-Identifier: GPL-2.0+
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* */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gic.h>
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#include <sys_config.h>
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#include <fdt_support.h>
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#include "sunxi-ir.h"
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#include "asm/arch/timer.h"
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DECLARE_GLOBAL_DATA_PTR;
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DEFINE_IR_RAW_EVENT(rawir);
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struct ir_raw_buffer sunxi_ir_raw;
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static bool pluse_pre;
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static u32 is_receiving;
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extern struct timer_list ir_timer_t;
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static inline void ir_reset_rawbuffer(void)
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{
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sunxi_ir_raw.dcnt = 0;
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}
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static inline u8 ir_get_data(void)
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{
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return (u8)(readl(IR_BASE + IR_RXDAT_REG));
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}
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static inline u32 ir_get_intsta(void)
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{
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return readl(IR_BASE + IR_RXINTS_REG);
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}
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static inline void ir_clr_intsta(u32 bitmap)
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{
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u32 tmp = readl(IR_BASE + IR_RXINTS_REG);
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tmp &= ~0xff;
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tmp |= bitmap & 0xff;
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writel(tmp, IR_BASE + IR_RXINTS_REG);
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}
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static void ir_mode_set(enum ir_mode set_mode)
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{
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u32 ctrl_reg = 0;
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switch (set_mode) {
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case CIR_MODE_ENABLE:
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ctrl_reg = readl(IR_BASE + IR_CTRL_REG);
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ctrl_reg |= IR_CIR_MODE; /* //(0x3<<4) */
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break;
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case IR_MODULE_ENABLE:
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ctrl_reg = readl(IR_BASE + IR_CTRL_REG);
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ctrl_reg |= IR_ENTIRE_ENABLE; /* //(0x3<<0) */
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break;
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default:
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return;
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}
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writel(ctrl_reg, IR_BASE + IR_CTRL_REG);
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}
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static void ir_sample_config(enum ir_sample_config set_sample)
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{
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u32 sample_reg = 0;
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sample_reg = readl(IR_BASE + IR_SPLCFG_REG);
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switch (set_sample) {
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case IR_SAMPLE_REG_CLEAR:
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sample_reg = 0;
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break;
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case IR_CLK_SAMPLE:
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sample_reg |= IR_SAMPLE_DEV; /* //(0x3<<0) */
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break;
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case IR_FILTER_TH:
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sample_reg |= IR_RXFILT_VAL;
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break;
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case IR_IDLE_TH:
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sample_reg |= IR_RXIDLE_VAL;
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break;
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case IR_ACTIVE_TH:
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sample_reg |= IR_ACTIVE_T;
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sample_reg |= IR_ACTIVE_T_C;
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break;
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default:
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return;
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}
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writel(sample_reg, IR_BASE + IR_SPLCFG_REG);
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}
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static void ir_signal_invert(void)
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{
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u32 reg_value;
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reg_value = 0x1 << 2;
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writel(reg_value, IR_BASE + IR_RXCFG_REG);
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}
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static void ir_irq_config(enum ir_irq_config set_irq)
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{
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u32 irq_reg = 0;
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switch (set_irq) {
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case IR_IRQ_STATUS_CLEAR:
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writel(0xef, IR_BASE + IR_RXINTS_REG);
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return;
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case IR_IRQ_ENABLE:
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irq_reg = readl(IR_BASE + IR_RXINTE_REG);
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irq_reg |= IR_IRQ_STATUS;
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break;
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case IR_IRQ_FIFO_SIZE:
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irq_reg = readl(IR_BASE + IR_RXINTE_REG);
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irq_reg |= IR_FIFO_32;
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break;
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default:
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return;
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}
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writel(irq_reg, IR_BASE + IR_RXINTE_REG);
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}
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static void ir_reg_cfg(void)
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{
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/* Enable IR Mode */
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ir_mode_set(CIR_MODE_ENABLE);
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/* Config IR Smaple Register */
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ir_sample_config(IR_SAMPLE_REG_CLEAR);
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ir_sample_config(IR_CLK_SAMPLE);
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ir_sample_config(IR_FILTER_TH); /* Set Filter Threshold */
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ir_sample_config(IR_IDLE_TH); /* Set Idle Threshold */
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ir_sample_config(IR_ACTIVE_TH); /* Set Active Threshold */
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/* Invert Input Signal */
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ir_signal_invert();
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/* Clear All Rx Interrupt Status */
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ir_irq_config(IR_IRQ_STATUS_CLEAR);
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/* Set Rx Interrupt Enable */
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ir_irq_config(IR_IRQ_ENABLE);
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ir_irq_config(IR_IRQ_FIFO_SIZE); /* Rx FIFO Threshold = FIFOsz/2; */
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/* Enable IR Module */
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ir_mode_set(IR_MODULE_ENABLE);
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}
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static int ir_raw_event_store(struct ir_raw_buffer *ir_raw,
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struct ir_raw_event *ev)
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{
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if (ir_raw->dcnt < IR_RAW_BUF_SIZE)
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memcpy(&(ir_raw->raw[ir_raw->dcnt++]), ev, sizeof(*ev));
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else
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print_debug("raw event store full\n");
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return 0;
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}
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__weak unsigned long ir_packet_handle(struct ir_raw_buffer *ir_raw)
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{
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return 0;
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}
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void ir_recv_irq_service(void *data)
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{
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u32 intsta, dcnt;
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u32 i = 0;
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bool pluse_now = 0;
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u8 reg_data;
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print_debug("IR RX IRQ Serve\n");
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intsta = ir_get_intsta();
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ir_clr_intsta(intsta);
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dcnt = (ir_get_intsta() >> 8) & 0x7f;
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print_debug("receive cnt :%d \n", dcnt);
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/* Read FIFO and fill the raw event */
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{
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/* get the data from fifo */
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for (i = 0; i < dcnt; i++) {
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reg_data = ir_get_data();
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pluse_now = (reg_data & 0x80) ? true : false;
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if (pluse_pre == pluse_now) { /* the signal maintian */
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/* the pluse or space lasting*/
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rawir.duration += (u32)(reg_data & 0x7f);
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print_debug("raw: %d:%d \n",
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(reg_data & 0x80) >> 7,
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(reg_data & 0x7f));
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} else {
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if (is_receiving) {
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rawir.duration *= IR_SIMPLE_UNIT;
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print_debug("pusle :%d, dur: %u ns\n",
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rawir.pulse,
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rawir.duration);
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ir_raw_event_store(&sunxi_ir_raw,
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&rawir);
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rawir.pulse = pluse_now;
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rawir.duration = (u32)(reg_data & 0x7f);
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print_debug("raw: %d:%d \n",
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(reg_data & 0x80) >> 7,
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(reg_data & 0x7f));
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} else {
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/* get the first pluse signal */
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rawir.pulse = pluse_now;
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rawir.duration = (u32)(reg_data & 0x7f);
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#ifdef CIR_24M_CLK_USED
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rawir.duration +=
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((IR_ACTIVE_T >> 16) + 1) *
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((IR_ACTIVE_T_C >> 23) ? 128 :
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1);
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print_debug(
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"get frist pulse,add head %d !!\n",
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((IR_ACTIVE_T >> 16) + 1) *
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((IR_ACTIVE_T_C >> 23) ?
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128 :
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1));
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#endif
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is_receiving = 1;
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print_debug("raw: %d:%d \n",
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(reg_data & 0x80) >> 7,
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(reg_data & 0x7f));
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}
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pluse_pre = pluse_now;
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}
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}
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}
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if (intsta & IR_RXINTS_RXPE) { /* Packet End */
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if (rawir.duration) {
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rawir.duration *= IR_SIMPLE_UNIT;
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print_debug("pusle :%d, dur: %u ns\n", rawir.pulse,
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rawir.duration);
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ir_raw_event_store(&sunxi_ir_raw, &rawir);
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}
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print_debug("handle raw data.\n");
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/* handle ther decoder theread */
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ir_packet_handle(&sunxi_ir_raw);
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ir_reset_rawbuffer();
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is_receiving = 0;
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pluse_pre = false;
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}
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if (intsta & IR_RXINTS_RXOF) { /* FIFO Overflow */
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/* flush rew buffer */
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is_receiving = 0;
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pluse_pre = false;
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ir_reset_rawbuffer();
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printf("ir_irq_service: Rx FIFO Overflow\n");
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}
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print_debug("ir_irq_service: end\n");
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return;
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}
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void rc_keydown(struct ir_raw_buffer *ir_raw, u32 scancode, u8 toggle)
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{
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ir_raw->scancode = scancode;
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}
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int ir_setup(void)
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{
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if (fdt_set_all_pin("/soc/s_cir", "pinctrl-0")) {
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printf("[ir_boot_para] ir gpio failed\n");
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return -1;
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}
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ir_clk_cfg();
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ir_reg_cfg();
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ir_reset_rawbuffer();
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irq_install_handler(AW_IRQ_CIR, ir_recv_irq_service, NULL);
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irq_enable(AW_IRQ_CIR);
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return 0;
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}
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void ir_disable(void)
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{
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irq_disable(AW_IRQ_CIR);
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irq_free_handler(AW_IRQ_CIR);
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}
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