/*
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* (C) Copyright 2013-2016
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ce.h>
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static int ss_base_mode;
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__weak u32 ss_get_addr_align(void)
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{
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#if defined(CONFIG_MACH_SUN50IW10)
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return 2; /*addr must be word align, for aceess 4G space of ddr*/
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#else
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return 0;
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#endif
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}
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__weak int ss_get_ver(void)
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{
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#ifdef SS_VER
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/* CE 2.1 */
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u8 val = (readl(SS_VER) >> 8) & 0xf;
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return val;
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#else
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return 0;
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#endif
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}
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__weak void ss_set_drq(u32 addr)
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{
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writel(addr, SS_TDQ);
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}
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__weak void ss_ctrl_start(u8 alg_type)
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{
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u32 val = 0;
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while ((readl(SS_TLR) & (0x1 << alg_type)) == 1) {
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};
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val = readl(SS_TLR);
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val |= (0x1 << alg_type);
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writel(val, SS_TLR);
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}
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__weak void ss_ctrl_stop(void)
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{
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writel(0x0, SS_TLR);
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}
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__weak u32 ss_check_err(u32 channel_id)
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{
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return (readl(SS_ERR) & (0xff << channel_id));
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}
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__weak void ss_wait_finish(u32 task_id)
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{
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uint int_en;
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int_en = readl(SS_ICR) & 0xf;
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int_en = int_en & (0x01 << task_id);
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if (int_en != 0) {
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while ((readl(SS_ISR) & (0x01 << task_id * 2)) == 0) {
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;
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}
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}
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}
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__weak u32 ss_pending_clear(u32 task_id)
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{
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u32 reg_val;
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u32 res, ret = 0;
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reg_val = readl(SS_ISR);
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res = reg_val & (0x3 << task_id * 2);
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if (res == 0x1) {
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ret = 0;
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} else if (res == 0x2) {
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ret = ss_check_err(task_id);
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}
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reg_val = (reg_val & 0xff) | (0x3 << task_id * 2);
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writel(reg_val, SS_ISR);
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writel(0x0, SS_ICR);
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return ret;
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}
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__weak void ss_irq_enable(u32 task_id)
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{
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int val = readl(SS_ICR);
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val |= (0x1 << task_id);
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writel(val, SS_ICR);
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}
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__weak void ss_irq_disable(u32 task_id)
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{
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int val = readl(SS_ICR);
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val &= ~(1 << task_id);
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writel(val, SS_ICR);
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}
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__weak void ss_open(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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u32 reg_val;
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static int initd;
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if (initd)
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return;
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initd = 1;
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reg_val = readl(&ccm->ce_clk_cfg); /*ce CLOCK*/
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reg_val &= (~((0x3 << 8) | (0xf << 0)));
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reg_val |= (0x0 << 0);
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writel(reg_val, &ccm->ce_clk_cfg);
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reg_val = readl(&ccm->ce_clk_cfg);
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#if defined(CONFIG_SUNXI_VERSION1)
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/* enable SS working clock */
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reg_val = readl(&ccm->ss_clk_cfg); /* SS CLOCK */
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reg_val &= ~(0xf << 24);
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reg_val |= 0x1 << 24;
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reg_val &= ~(0x3 << 16);
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reg_val |= 0x0 << 16;
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reg_val &= ~(0xf);
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reg_val |= (4 - 1);
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reg_val |= 0x1U << 31;
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writel(reg_val, &ccm->ss_clk_cfg);
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/* enable SS AHB clock */
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reg_val = readl(&ccm->ahb_gate0);
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reg_val |= 0x1 << 5; /* SS AHB clock on */
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writel(reg_val, &ccm->ahb_gate0);
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/* del-assert SS reset */
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reg_val = readl(&ccm->ahb_reset0_cfg);
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reg_val |= 0x1 << 5; /* SS AHB clock reset */
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writel(reg_val, &ccm->ahb_reset0_cfg);
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#else
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reg_val = readl(&ccm->ce_clk_cfg);
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/*set CE src clock*/
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reg_val &= ~(CE_CLK_SRC_MASK << CE_CLK_SRC_SEL_BIT);
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udelay(10);
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#ifdef FPGA_PLATFORM
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/* OSC24M */
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reg_val |= 0 << CE_CLK_SRC_SEL_BIT;
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#else
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reg_val |= CE_CLK_SRC << CE_CLK_SRC_SEL_BIT;
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/*set div n*/
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reg_val &= ~(CE_CLK_DIV_RATION_N_MASK << CE_CLK_DIV_RATION_N_BIT);
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reg_val |= CE_CLK_DIV_RATION_N << CE_CLK_DIV_RATION_N_BIT;
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/*set div m*/
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reg_val &= ~(CE_CLK_DIV_RATION_M_MASK << CE_CLK_DIV_RATION_M_BIT);
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reg_val |= CE_CLK_DIV_RATION_M << CE_CLK_DIV_RATION_M_BIT;
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#endif
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/*set src clock on*/
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reg_val |= CE_SCLK_ON << CE_SCLK_ONOFF_BIT;
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writel(reg_val, &ccm->ce_clk_cfg);
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/*open CE gating*/
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reg_val = readl(&ccm->ce_gate_reset);
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reg_val |= CE_GATING_PASS << CE_GATING_BIT;
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writel(reg_val, &ccm->ce_gate_reset);
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reg_val = readl(&ccm->mbus_gate);
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reg_val &= ~(CE_MBUS_GATING_MASK << CE_MBUS_GATING_BIT);
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reg_val |= CE_MBUS_GATING << CE_MBUS_GATING_BIT;
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writel(reg_val, &ccm->mbus_gate);
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/*de-assert*/
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reg_val = readl(&ccm->ce_gate_reset);
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reg_val |= CE_DEASSERT << CE_RST_BIT;
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writel(reg_val, &ccm->ce_gate_reset);
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#endif
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}
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__weak void ss_close(void)
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{
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}
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