// SPDX-License-Identifier: GPL-2.0+
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/*
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* Socfpga Reset Controller Driver
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*
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* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* based on
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* Allwinner SoCs Reset Controller driver
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*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/of_access.h>
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#include <reset-uclass.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#define BANK_INCREMENT 4
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#define NR_BANKS 8
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struct socfpga_reset_data {
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void __iomem *membase;
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};
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static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
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{
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struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
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int id = reset_ctl->id;
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
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return 0;
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}
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static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
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{
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struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
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int id = reset_ctl->id;
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
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return 0;
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}
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static int socfpga_reset_request(struct reset_ctl *reset_ctl)
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{
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
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reset_ctl, reset_ctl->dev, reset_ctl->id);
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return 0;
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}
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static int socfpga_reset_free(struct reset_ctl *reset_ctl)
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{
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debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
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reset_ctl->dev, reset_ctl->id);
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return 0;
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}
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static const struct reset_ops socfpga_reset_ops = {
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.request = socfpga_reset_request,
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.free = socfpga_reset_free,
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.rst_assert = socfpga_reset_assert,
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.rst_deassert = socfpga_reset_deassert,
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};
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static int socfpga_reset_probe(struct udevice *dev)
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{
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struct socfpga_reset_data *data = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(dev);
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u32 modrst_offset;
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data->membase = devfdt_get_addr_ptr(dev);
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modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
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data->membase += modrst_offset;
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return 0;
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}
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static const struct udevice_id socfpga_reset_match[] = {
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{ .compatible = "altr,rst-mgr" },
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{ /* sentinel */ },
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};
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U_BOOT_DRIVER(socfpga_reset) = {
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.name = "socfpga-reset",
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.id = UCLASS_RESET,
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.of_match = socfpga_reset_match,
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.probe = socfpga_reset_probe,
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.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
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.ops = &socfpga_reset_ops,
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};
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