// Copyright 2014, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <cmath>
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#include "test-runner.h"
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#include "test-utils-aarch64.h"
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#include "aarch64/cpu-aarch64.h"
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/macro-assembler-aarch64.h"
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#include "aarch64/simulator-aarch64.h"
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#define __ masm->
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namespace vixl {
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namespace aarch64 {
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// This value is a signalling NaN as both a double and as a float (taking the
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// least-significant word).
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const double kFP64SignallingNaN = RawbitsToDouble(UINT64_C(0x7ff000007f800001));
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const float kFP32SignallingNaN = RawbitsToFloat(0x7f800001);
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const Float16 kFP16SignallingNaN = RawbitsToFloat16(0x7c01);
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// A similar value, but as a quiet NaN.
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const double kFP64QuietNaN = RawbitsToDouble(UINT64_C(0x7ff800007fc00001));
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const float kFP32QuietNaN = RawbitsToFloat(0x7fc00001);
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const Float16 kFP16QuietNaN = RawbitsToFloat16(0x7e01);
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bool Equal32(uint32_t expected, const RegisterDump*, uint32_t result) {
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if (result != expected) {
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printf("Expected 0x%08" PRIx32 "\t Found 0x%08" PRIx32 "\n",
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expected,
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result);
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}
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return expected == result;
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}
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bool Equal64(uint64_t expected, const RegisterDump*, uint64_t result) {
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if (result != expected) {
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printf("Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
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expected,
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result);
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}
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return expected == result;
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}
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bool Equal128(vec128_t expected, const RegisterDump*, vec128_t result) {
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if ((result.h != expected.h) || (result.l != expected.l)) {
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printf("Expected 0x%016" PRIx64 "%016" PRIx64
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"\t "
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"Found 0x%016" PRIx64 "%016" PRIx64 "\n",
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expected.h,
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expected.l,
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result.h,
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result.l);
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}
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return ((expected.h == result.h) && (expected.l == result.l));
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}
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bool EqualFP16(Float16 expected, const RegisterDump*, Float16 result) {
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uint16_t e_rawbits = Float16ToRawbits(expected);
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uint16_t r_rawbits = Float16ToRawbits(result);
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if (e_rawbits == r_rawbits) {
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return true;
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} else {
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if (IsNaN(expected) || IsZero(expected)) {
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printf("Expected 0x%04" PRIx16 "\t Found 0x%04" PRIx16 "\n",
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e_rawbits,
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r_rawbits);
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} else {
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printf("Expected %.6f (16 bit): (0x%04" PRIx16
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")\t "
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"Found %.6f (0x%04" PRIx16 ")\n",
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FPToFloat(expected, kIgnoreDefaultNaN),
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e_rawbits,
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FPToFloat(result, kIgnoreDefaultNaN),
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r_rawbits);
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}
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return false;
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}
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}
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bool EqualFP32(float expected, const RegisterDump*, float result) {
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if (FloatToRawbits(expected) == FloatToRawbits(result)) {
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return true;
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} else {
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if (IsNaN(expected) || (expected == 0.0)) {
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printf("Expected 0x%08" PRIx32 "\t Found 0x%08" PRIx32 "\n",
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FloatToRawbits(expected),
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FloatToRawbits(result));
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} else {
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printf("Expected %.9f (0x%08" PRIx32
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")\t "
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"Found %.9f (0x%08" PRIx32 ")\n",
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expected,
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FloatToRawbits(expected),
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result,
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FloatToRawbits(result));
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}
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return false;
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}
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}
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bool EqualFP64(double expected, const RegisterDump*, double result) {
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if (DoubleToRawbits(expected) == DoubleToRawbits(result)) {
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return true;
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}
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if (IsNaN(expected) || (expected == 0.0)) {
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printf("Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
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DoubleToRawbits(expected),
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DoubleToRawbits(result));
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} else {
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printf("Expected %.17f (0x%016" PRIx64
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")\t "
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"Found %.17f (0x%016" PRIx64 ")\n",
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expected,
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DoubleToRawbits(expected),
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result,
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DoubleToRawbits(result));
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}
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return false;
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}
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bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) {
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VIXL_ASSERT(reg.Is32Bits());
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// Retrieve the corresponding X register so we can check that the upper part
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// was properly cleared.
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int64_t result_x = core->xreg(reg.GetCode());
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if ((result_x & 0xffffffff00000000) != 0) {
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printf("Expected 0x%08" PRIx32 "\t Found 0x%016" PRIx64 "\n",
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expected,
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result_x);
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return false;
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}
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uint32_t result_w = core->wreg(reg.GetCode());
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return Equal32(expected, core, result_w);
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}
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bool Equal64(uint64_t expected, const RegisterDump* core, const Register& reg) {
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VIXL_ASSERT(reg.Is64Bits());
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uint64_t result = core->xreg(reg.GetCode());
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return Equal64(expected, core, result);
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}
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bool Equal128(uint64_t expected_h,
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uint64_t expected_l,
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const RegisterDump* core,
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const VRegister& vreg) {
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VIXL_ASSERT(vreg.Is128Bits());
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vec128_t expected = {expected_l, expected_h};
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vec128_t result = core->qreg(vreg.GetCode());
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return Equal128(expected, core, result);
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}
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bool EqualFP16(Float16 expected,
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const RegisterDump* core,
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const FPRegister& fpreg) {
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VIXL_ASSERT(fpreg.Is16Bits());
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// Retrieve the corresponding D register so we can check that the upper part
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// was properly cleared.
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uint64_t result_64 = core->dreg_bits(fpreg.GetCode());
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if ((result_64 & 0xfffffffffff0000) != 0) {
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printf("Expected 0x%04" PRIx16 " (%f)\t Found 0x%016" PRIx64 "\n",
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Float16ToRawbits(expected),
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FPToFloat(expected, kIgnoreDefaultNaN),
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result_64);
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return false;
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}
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return EqualFP16(expected, core, core->hreg(fpreg.GetCode()));
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}
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bool EqualFP32(float expected,
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const RegisterDump* core,
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const FPRegister& fpreg) {
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VIXL_ASSERT(fpreg.Is32Bits());
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// Retrieve the corresponding D register so we can check that the upper part
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// was properly cleared.
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uint64_t result_64 = core->dreg_bits(fpreg.GetCode());
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if ((result_64 & 0xffffffff00000000) != 0) {
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printf("Expected 0x%08" PRIx32 " (%f)\t Found 0x%016" PRIx64 "\n",
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FloatToRawbits(expected),
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expected,
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result_64);
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return false;
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}
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return EqualFP32(expected, core, core->sreg(fpreg.GetCode()));
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}
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bool EqualFP64(double expected,
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const RegisterDump* core,
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const FPRegister& fpreg) {
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VIXL_ASSERT(fpreg.Is64Bits());
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return EqualFP64(expected, core, core->dreg(fpreg.GetCode()));
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}
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bool Equal64(const Register& reg0,
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const RegisterDump* core,
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const Register& reg1) {
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VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
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int64_t expected = core->xreg(reg0.GetCode());
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int64_t result = core->xreg(reg1.GetCode());
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return Equal64(expected, core, result);
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}
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bool Equal64(uint64_t expected,
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const RegisterDump* core,
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const VRegister& vreg) {
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VIXL_ASSERT(vreg.Is64Bits());
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uint64_t result = core->dreg_bits(vreg.GetCode());
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return Equal64(expected, core, result);
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}
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static char FlagN(uint32_t flags) { return (flags & NFlag) ? 'N' : 'n'; }
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static char FlagZ(uint32_t flags) { return (flags & ZFlag) ? 'Z' : 'z'; }
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static char FlagC(uint32_t flags) { return (flags & CFlag) ? 'C' : 'c'; }
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static char FlagV(uint32_t flags) { return (flags & VFlag) ? 'V' : 'v'; }
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bool EqualNzcv(uint32_t expected, uint32_t result) {
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VIXL_ASSERT((expected & ~NZCVFlag) == 0);
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VIXL_ASSERT((result & ~NZCVFlag) == 0);
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if (result != expected) {
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printf("Expected: %c%c%c%c\t Found: %c%c%c%c\n",
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FlagN(expected),
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FlagZ(expected),
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FlagC(expected),
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FlagV(expected),
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FlagN(result),
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FlagZ(result),
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FlagC(result),
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FlagV(result));
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return false;
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}
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return true;
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}
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bool EqualRegisters(const RegisterDump* a, const RegisterDump* b) {
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for (unsigned i = 0; i < kNumberOfRegisters; i++) {
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if (a->xreg(i) != b->xreg(i)) {
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printf("x%d\t Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
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i,
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a->xreg(i),
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b->xreg(i));
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return false;
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}
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}
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for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
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uint64_t a_bits = a->dreg_bits(i);
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uint64_t b_bits = b->dreg_bits(i);
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if (a_bits != b_bits) {
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printf("d%d\t Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
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i,
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a_bits,
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b_bits);
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return false;
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}
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}
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return true;
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}
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RegList PopulateRegisterArray(Register* w,
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Register* x,
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Register* r,
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int reg_size,
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int reg_count,
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RegList allowed) {
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RegList list = 0;
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int i = 0;
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for (unsigned n = 0; (n < kNumberOfRegisters) && (i < reg_count); n++) {
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if (((UINT64_C(1) << n) & allowed) != 0) {
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// Only assign allowed registers.
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if (r) {
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r[i] = Register(n, reg_size);
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}
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if (x) {
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x[i] = Register(n, kXRegSize);
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}
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if (w) {
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w[i] = Register(n, kWRegSize);
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}
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list |= (UINT64_C(1) << n);
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i++;
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}
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}
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// Check that we got enough registers.
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VIXL_ASSERT(CountSetBits(list, kNumberOfRegisters) == reg_count);
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return list;
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}
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RegList PopulateFPRegisterArray(FPRegister* s,
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FPRegister* d,
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FPRegister* v,
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int reg_size,
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int reg_count,
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RegList allowed) {
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RegList list = 0;
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int i = 0;
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for (unsigned n = 0; (n < kNumberOfFPRegisters) && (i < reg_count); n++) {
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if (((UINT64_C(1) << n) & allowed) != 0) {
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// Only assigned allowed registers.
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if (v) {
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v[i] = FPRegister(n, reg_size);
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}
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if (d) {
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d[i] = FPRegister(n, kDRegSize);
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}
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if (s) {
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s[i] = FPRegister(n, kSRegSize);
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}
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list |= (UINT64_C(1) << n);
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i++;
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}
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}
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// Check that we got enough registers.
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VIXL_ASSERT(CountSetBits(list, kNumberOfFPRegisters) == reg_count);
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return list;
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}
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void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) {
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Register first = NoReg;
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for (unsigned i = 0; i < kNumberOfRegisters; i++) {
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if (reg_list & (UINT64_C(1) << i)) {
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Register xn(i, kXRegSize);
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// We should never write into sp here.
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VIXL_ASSERT(!xn.Is(sp));
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if (!xn.IsZero()) {
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if (!first.IsValid()) {
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// This is the first register we've hit, so construct the literal.
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__ Mov(xn, value);
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first = xn;
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} else {
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// We've already loaded the literal, so re-use the value already
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// loaded into the first register we hit.
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__ Mov(xn, first);
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}
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}
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}
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}
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}
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void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) {
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FPRegister first = NoFPReg;
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for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
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if (reg_list & (UINT64_C(1) << i)) {
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FPRegister dn(i, kDRegSize);
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if (!first.IsValid()) {
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// This is the first register we've hit, so construct the literal.
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__ Fmov(dn, value);
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first = dn;
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} else {
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// We've already loaded the literal, so re-use the value already loaded
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// into the first register we hit.
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__ Fmov(dn, first);
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}
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}
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}
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}
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void Clobber(MacroAssembler* masm, CPURegList reg_list) {
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if (reg_list.GetType() == CPURegister::kRegister) {
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// This will always clobber X registers.
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Clobber(masm, reg_list.GetList());
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} else if (reg_list.GetType() == CPURegister::kVRegister) {
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// This will always clobber D registers.
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ClobberFP(masm, reg_list.GetList());
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} else {
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VIXL_UNREACHABLE();
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}
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}
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void RegisterDump::Dump(MacroAssembler* masm) {
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VIXL_ASSERT(__ StackPointer().Is(sp));
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// Ensure that we don't unintentionally clobber any registers.
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UseScratchRegisterScope temps(masm);
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temps.ExcludeAll();
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// Preserve some temporary registers.
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Register dump_base = x0;
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Register dump = x1;
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Register tmp = x2;
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Register dump_base_w = dump_base.W();
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Register dump_w = dump.W();
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Register tmp_w = tmp.W();
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// Offsets into the dump_ structure.
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const int x_offset = offsetof(dump_t, x_);
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const int w_offset = offsetof(dump_t, w_);
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const int d_offset = offsetof(dump_t, d_);
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const int s_offset = offsetof(dump_t, s_);
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const int h_offset = offsetof(dump_t, h_);
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const int q_offset = offsetof(dump_t, q_);
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const int sp_offset = offsetof(dump_t, sp_);
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const int wsp_offset = offsetof(dump_t, wsp_);
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const int flags_offset = offsetof(dump_t, flags_);
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__ Push(xzr, dump_base, dump, tmp);
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// Load the address where we will dump the state.
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__ Mov(dump_base, reinterpret_cast<uintptr_t>(&dump_));
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// Dump the stack pointer (sp and wsp).
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// The stack pointer cannot be stored directly; it needs to be moved into
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// another register first. Also, we pushed four X registers, so we need to
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// compensate here.
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__ Add(tmp, sp, 4 * kXRegSizeInBytes);
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__ Str(tmp, MemOperand(dump_base, sp_offset));
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__ Add(tmp_w, wsp, 4 * kXRegSizeInBytes);
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__ Str(tmp_w, MemOperand(dump_base, wsp_offset));
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// Dump X registers.
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__ Add(dump, dump_base, x_offset);
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for (unsigned i = 0; i < kNumberOfRegisters; i += 2) {
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__ Stp(Register::GetXRegFromCode(i),
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Register::GetXRegFromCode(i + 1),
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MemOperand(dump, i * kXRegSizeInBytes));
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}
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// Dump W registers.
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__ Add(dump, dump_base, w_offset);
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for (unsigned i = 0; i < kNumberOfRegisters; i += 2) {
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__ Stp(Register::GetWRegFromCode(i),
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Register::GetWRegFromCode(i + 1),
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MemOperand(dump, i * kWRegSizeInBytes));
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}
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// Dump D registers.
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__ Add(dump, dump_base, d_offset);
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for (unsigned i = 0; i < kNumberOfFPRegisters; i += 2) {
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__ Stp(FPRegister::GetDRegFromCode(i),
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FPRegister::GetDRegFromCode(i + 1),
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MemOperand(dump, i * kDRegSizeInBytes));
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}
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// Dump S registers.
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__ Add(dump, dump_base, s_offset);
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for (unsigned i = 0; i < kNumberOfFPRegisters; i += 2) {
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__ Stp(FPRegister::GetSRegFromCode(i),
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FPRegister::GetSRegFromCode(i + 1),
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MemOperand(dump, i * kSRegSizeInBytes));
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}
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#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
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// Dump H registers. Note: Stp does not support 16 bits.
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__ Add(dump, dump_base, h_offset);
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for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
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__ Str(FPRegister::GetHRegFromCode(i),
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MemOperand(dump, i * kHRegSizeInBytes));
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}
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#else
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USE(h_offset);
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#endif
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// Dump Q registers.
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__ Add(dump, dump_base, q_offset);
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for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
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__ Stp(VRegister::GetQRegFromCode(i),
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VRegister::GetQRegFromCode(i + 1),
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MemOperand(dump, i * kQRegSizeInBytes));
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}
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// Dump the flags.
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__ Mrs(tmp, NZCV);
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__ Str(tmp, MemOperand(dump_base, flags_offset));
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// To dump the values that were in tmp amd dump, we need a new scratch
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// register. We can use any of the already dumped registers since we can
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// easily restore them.
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Register dump2_base = x10;
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Register dump2 = x11;
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VIXL_ASSERT(!AreAliased(dump_base, dump, tmp, dump2_base, dump2));
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// Don't lose the dump_ address.
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__ Mov(dump2_base, dump_base);
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__ Pop(tmp, dump, dump_base, xzr);
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__ Add(dump2, dump2_base, w_offset);
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__ Str(dump_base_w,
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MemOperand(dump2, dump_base.GetCode() * kWRegSizeInBytes));
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__ Str(dump_w, MemOperand(dump2, dump.GetCode() * kWRegSizeInBytes));
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__ Str(tmp_w, MemOperand(dump2, tmp.GetCode() * kWRegSizeInBytes));
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__ Add(dump2, dump2_base, x_offset);
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__ Str(dump_base, MemOperand(dump2, dump_base.GetCode() * kXRegSizeInBytes));
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__ Str(dump, MemOperand(dump2, dump.GetCode() * kXRegSizeInBytes));
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__ Str(tmp, MemOperand(dump2, tmp.GetCode() * kXRegSizeInBytes));
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// Finally, restore dump2_base and dump2.
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__ Ldr(dump2_base,
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MemOperand(dump2, dump2_base.GetCode() * kXRegSizeInBytes));
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__ Ldr(dump2, MemOperand(dump2, dump2.GetCode() * kXRegSizeInBytes));
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completed_ = true;
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}
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} // namespace aarch64
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} // namespace vixl
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