/* Copyright 2015 The TensorFlow Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#include "tensorflow/cc/ops/const_op.h"
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#include "tensorflow/cc/ops/image_ops.h"
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#include "tensorflow/cc/ops/nn_ops.h"
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#include "tensorflow/cc/ops/standard_ops.h"
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#include "tensorflow/core/common_runtime/kernel_benchmark_testlib.h"
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#include "tensorflow/core/framework/fake_input.h"
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#include "tensorflow/core/framework/node_def_builder.h"
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#include "tensorflow/core/framework/tensor.h"
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#include "tensorflow/core/framework/types.h"
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#include "tensorflow/core/kernels/conv_ops_gpu.h"
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#include "tensorflow/core/kernels/ops_testutil.h"
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#include "tensorflow/core/kernels/ops_util.h"
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#include "tensorflow/core/platform/test.h"
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#include "tensorflow/core/platform/test_benchmark.h"
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#include "tensorflow/core/public/session.h"
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namespace tensorflow {
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namespace {
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class DepthwiseConvOpTest : public OpsTestBase {
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protected:
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enum class Device { CPU, GPU };
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template <typename T>
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void Run(Device device) {
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if (device == Device::GPU) {
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SetDevice(DEVICE_GPU,
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std::unique_ptr<tensorflow::Device>(DeviceFactory::NewDevice(
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"GPU", {}, "/job:a/replica:0/task:0")));
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}
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DataType dtype = DataTypeToEnum<T>::value;
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TF_EXPECT_OK(NodeDefBuilder("depthwise_conv2d", "DepthwiseConv2dNative")
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.Input(FakeInput(dtype))
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.Input(FakeInput(dtype))
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.Attr("T", dtype)
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.Attr("strides", {1, 1, 1, 1})
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.Attr("padding", "SAME")
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.Finalize(node_def()));
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TF_EXPECT_OK(InitOp());
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const int depth = 2;
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const int image_width = 2;
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const int image_height = 3;
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const int batch_count = 1;
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// The image matrix is ('first/second' channel):
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// | 1/2 | 3/4 |
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// | 5/6 | 7/8 |
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// | 9/10 | 11/12 |
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Tensor image(dtype, {batch_count, image_height, image_width, depth});
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test::FillValues<T>(&image, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12});
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// The filter matrix is:
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// | 1/2 | 7/8 | 13/14 |
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// | 3/4 | 9/10 | 15/16 |
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// | 5/6 | 11/12 | 17/18 |
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const int filter_size = 3;
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const int filter_count = 1;
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Tensor filter(dtype, {filter_size, filter_size, depth, filter_count});
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test::FillValues<T>(&filter, {1, 2, 7, 8, 13, 14, 3, 4, 9, 10, 15, 16, 5, 6,
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11, 12, 17, 18});
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AddInputFromArray<T>(image.shape(), image.flat<T>());
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AddInputFromArray<T>(filter.shape(), filter.flat<T>());
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TF_ASSERT_OK(RunOpKernel());
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// We're sliding two 3x3 filters across the 3x2 image, with accesses outside
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// the input set to zero because we're using the 'SAME' padding mode.
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// This means we should end up with this matrix:
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// | 105/150 | 183/95 |
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// | 235/312 | 357/178 |
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// | 187/234 | 261/121 |
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Tensor expected(dtype, image.shape());
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test::FillValues<T>(&expected, {228, 300, 132, 180, 482, 596, 266, 344, 372,
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452, 180, 236});
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const Tensor& output = *GetOutput(0);
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// TODO(csigg): This should happen as part of GetOutput.
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TF_EXPECT_OK(device_->Sync());
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test::ExpectTensorNear<T>(expected, output, 1e-5);
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}
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};
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TEST_F(DepthwiseConvOpTest, DepthwiseConvFloatCpu) { Run<float>(Device::CPU); }
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TEST_F(DepthwiseConvOpTest, DepthwiseConvDoubleCpu) {
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Run<double>(Device::CPU);
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}
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TEST_F(DepthwiseConvOpTest, DepthwiseConvHalfCpu) {
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Run<Eigen::half>(Device::CPU);
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}
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#ifdef GOOGLE_CUDA
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TEST_F(DepthwiseConvOpTest, DepthwiseConvFloatGpu) { Run<float>(Device::GPU); }
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TEST_F(DepthwiseConvOpTest, DepthwiseConvDoubleGpu) {
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Run<double>(Device::GPU);
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}
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TEST_F(DepthwiseConvOpTest, DepthwiseConvHalfGpu) {
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Run<Eigen::half>(Device::GPU);
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}
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#endif
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} // namespace
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} // namespace tensorflow
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