// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package x86
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import (
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"fmt"
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"math"
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"cmd/compile/internal/gc"
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"cmd/compile/internal/ssa"
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"cmd/compile/internal/types"
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"cmd/internal/obj"
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"cmd/internal/obj/x86"
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)
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// markMoves marks any MOVXconst ops that need to avoid clobbering flags.
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func ssaMarkMoves(s *gc.SSAGenState, b *ssa.Block) {
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flive := b.FlagsLiveAtEnd
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if b.Control != nil && b.Control.Type.IsFlags() {
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flive = true
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}
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for i := len(b.Values) - 1; i >= 0; i-- {
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v := b.Values[i]
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if flive && v.Op == ssa.Op386MOVLconst {
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// The "mark" is any non-nil Aux value.
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v.Aux = v
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}
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if v.Type.IsFlags() {
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flive = false
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}
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for _, a := range v.Args {
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if a.Type.IsFlags() {
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flive = true
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}
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}
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}
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}
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// loadByType returns the load instruction of the given type.
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func loadByType(t *types.Type) obj.As {
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// Avoid partial register write
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if !t.IsFloat() && t.Size() <= 2 {
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if t.Size() == 1 {
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return x86.AMOVBLZX
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} else {
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return x86.AMOVWLZX
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}
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}
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// Otherwise, there's no difference between load and store opcodes.
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return storeByType(t)
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}
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// storeByType returns the store instruction of the given type.
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func storeByType(t *types.Type) obj.As {
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width := t.Size()
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if t.IsFloat() {
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switch width {
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case 4:
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return x86.AMOVSS
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case 8:
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return x86.AMOVSD
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}
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} else {
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switch width {
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case 1:
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return x86.AMOVB
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case 2:
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return x86.AMOVW
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case 4:
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return x86.AMOVL
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}
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}
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panic("bad store type")
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}
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// moveByType returns the reg->reg move instruction of the given type.
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func moveByType(t *types.Type) obj.As {
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if t.IsFloat() {
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switch t.Size() {
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case 4:
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return x86.AMOVSS
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case 8:
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return x86.AMOVSD
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default:
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panic(fmt.Sprintf("bad float register width %d:%s", t.Size(), t))
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}
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} else {
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switch t.Size() {
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case 1:
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// Avoids partial register write
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return x86.AMOVL
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case 2:
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return x86.AMOVL
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case 4:
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return x86.AMOVL
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default:
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panic(fmt.Sprintf("bad int register width %d:%s", t.Size(), t))
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}
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}
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}
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// opregreg emits instructions for
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// dest := dest(To) op src(From)
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// and also returns the created obj.Prog so it
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// may be further adjusted (offset, scale, etc).
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func opregreg(s *gc.SSAGenState, op obj.As, dest, src int16) *obj.Prog {
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p := s.Prog(op)
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p.From.Type = obj.TYPE_REG
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p.To.Type = obj.TYPE_REG
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p.To.Reg = dest
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p.From.Reg = src
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return p
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}
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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switch v.Op {
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case ssa.Op386ADDL:
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r := v.Reg()
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r1 := v.Args[0].Reg()
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r2 := v.Args[1].Reg()
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switch {
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case r == r1:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r2
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case r == r2:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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default:
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p := s.Prog(x86.ALEAL)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = r1
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p.From.Scale = 1
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p.From.Index = r2
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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// 2-address opcode arithmetic
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case ssa.Op386SUBL,
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ssa.Op386MULL,
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ssa.Op386ANDL,
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ssa.Op386ORL,
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ssa.Op386XORL,
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ssa.Op386SHLL,
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ssa.Op386SHRL, ssa.Op386SHRW, ssa.Op386SHRB,
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ssa.Op386SARL, ssa.Op386SARW, ssa.Op386SARB,
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ssa.Op386ADDSS, ssa.Op386ADDSD, ssa.Op386SUBSS, ssa.Op386SUBSD,
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ssa.Op386MULSS, ssa.Op386MULSD, ssa.Op386DIVSS, ssa.Op386DIVSD,
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ssa.Op386PXOR,
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ssa.Op386ADCL,
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ssa.Op386SBBL:
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r := v.Reg()
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if r != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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opregreg(s, v.Op.Asm(), r, v.Args[1].Reg())
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case ssa.Op386ADDLcarry, ssa.Op386SUBLcarry:
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// output 0 is carry/borrow, output 1 is the low 32 bits.
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r := v.Reg0()
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if r != v.Args[0].Reg() {
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v.Fatalf("input[0] and output[0] not in same register %s", v.LongString())
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}
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opregreg(s, v.Op.Asm(), r, v.Args[1].Reg())
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case ssa.Op386ADDLconstcarry, ssa.Op386SUBLconstcarry:
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// output 0 is carry/borrow, output 1 is the low 32 bits.
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r := v.Reg0()
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if r != v.Args[0].Reg() {
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v.Fatalf("input[0] and output[0] not in same register %s", v.LongString())
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}
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.Op386DIVL, ssa.Op386DIVW,
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ssa.Op386DIVLU, ssa.Op386DIVWU,
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ssa.Op386MODL, ssa.Op386MODW,
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ssa.Op386MODLU, ssa.Op386MODWU:
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// Arg[0] is already in AX as it's the only register we allow
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// and AX is the only output
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x := v.Args[1].Reg()
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// CPU faults upon signed overflow, which occurs when most
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// negative int is divided by -1.
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var j *obj.Prog
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if v.Op == ssa.Op386DIVL || v.Op == ssa.Op386DIVW ||
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v.Op == ssa.Op386MODL || v.Op == ssa.Op386MODW {
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if ssa.NeedsFixUp(v) {
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var c *obj.Prog
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switch v.Op {
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case ssa.Op386DIVL, ssa.Op386MODL:
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c = s.Prog(x86.ACMPL)
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j = s.Prog(x86.AJEQ)
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case ssa.Op386DIVW, ssa.Op386MODW:
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c = s.Prog(x86.ACMPW)
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j = s.Prog(x86.AJEQ)
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}
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c.From.Type = obj.TYPE_REG
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c.From.Reg = x
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c.To.Type = obj.TYPE_CONST
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c.To.Offset = -1
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j.To.Type = obj.TYPE_BRANCH
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}
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// sign extend the dividend
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switch v.Op {
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case ssa.Op386DIVL, ssa.Op386MODL:
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s.Prog(x86.ACDQ)
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case ssa.Op386DIVW, ssa.Op386MODW:
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s.Prog(x86.ACWD)
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}
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}
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// for unsigned ints, we sign extend by setting DX = 0
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// signed ints were sign extended above
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if v.Op == ssa.Op386DIVLU || v.Op == ssa.Op386MODLU ||
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v.Op == ssa.Op386DIVWU || v.Op == ssa.Op386MODWU {
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c := s.Prog(x86.AXORL)
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c.From.Type = obj.TYPE_REG
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c.From.Reg = x86.REG_DX
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c.To.Type = obj.TYPE_REG
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c.To.Reg = x86.REG_DX
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}
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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// signed division, rest of the check for -1 case
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if j != nil {
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j2 := s.Prog(obj.AJMP)
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j2.To.Type = obj.TYPE_BRANCH
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var n *obj.Prog
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if v.Op == ssa.Op386DIVL || v.Op == ssa.Op386DIVW {
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// n * -1 = -n
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n = s.Prog(x86.ANEGL)
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n.To.Type = obj.TYPE_REG
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n.To.Reg = x86.REG_AX
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} else {
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// n % -1 == 0
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n = s.Prog(x86.AXORL)
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n.From.Type = obj.TYPE_REG
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n.From.Reg = x86.REG_DX
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n.To.Type = obj.TYPE_REG
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n.To.Reg = x86.REG_DX
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}
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j.To.Val = n
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j2.To.Val = s.Pc()
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}
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case ssa.Op386HMULL, ssa.Op386HMULLU:
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// the frontend rewrites constant division by 8/16/32 bit integers into
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// HMUL by a constant
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// SSA rewrites generate the 64 bit versions
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// Arg[0] is already in AX as it's the only register we allow
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// and DX is the only output we care about (the high bits)
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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// IMULB puts the high portion in AH instead of DL,
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// so move it to DL for consistency
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if v.Type.Size() == 1 {
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m := s.Prog(x86.AMOVB)
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m.From.Type = obj.TYPE_REG
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m.From.Reg = x86.REG_AH
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m.To.Type = obj.TYPE_REG
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m.To.Reg = x86.REG_DX
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}
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case ssa.Op386MULLU:
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// Arg[0] is already in AX as it's the only register we allow
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// results lo in AX
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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case ssa.Op386MULLQU:
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// AX * args[1], high 32 bits in DX (result[0]), low 32 bits in AX (result[1]).
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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case ssa.Op386AVGLU:
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// compute (x+y)/2 unsigned.
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// Do a 32-bit add, the overflow goes into the carry.
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// Shift right once and pull the carry back into the 31st bit.
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r := v.Reg()
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if r != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := s.Prog(x86.AADDL)
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p.From.Type = obj.TYPE_REG
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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p.From.Reg = v.Args[1].Reg()
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p = s.Prog(x86.ARCRL)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = 1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.Op386ADDLconst:
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r := v.Reg()
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a := v.Args[0].Reg()
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if r == a {
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if v.AuxInt == 1 {
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p := s.Prog(x86.AINCL)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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}
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if v.AuxInt == -1 {
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p := s.Prog(x86.ADECL)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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}
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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return
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}
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p := s.Prog(x86.ALEAL)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = a
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.Op386MULLconst:
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r := v.Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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p.SetFrom3(obj.Addr{Type: obj.TYPE_REG, Reg: v.Args[0].Reg()})
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case ssa.Op386SUBLconst,
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ssa.Op386ADCLconst,
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ssa.Op386SBBLconst,
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ssa.Op386ANDLconst,
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ssa.Op386ORLconst,
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ssa.Op386XORLconst,
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ssa.Op386SHLLconst,
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ssa.Op386SHRLconst, ssa.Op386SHRWconst, ssa.Op386SHRBconst,
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ssa.Op386SARLconst, ssa.Op386SARWconst, ssa.Op386SARBconst,
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ssa.Op386ROLLconst, ssa.Op386ROLWconst, ssa.Op386ROLBconst:
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r := v.Reg()
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if r != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.Op386SBBLcarrymask:
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r := v.Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.Op386LEAL1, ssa.Op386LEAL2, ssa.Op386LEAL4, ssa.Op386LEAL8:
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r := v.Args[0].Reg()
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i := v.Args[1].Reg()
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p := s.Prog(x86.ALEAL)
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switch v.Op {
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case ssa.Op386LEAL1:
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p.From.Scale = 1
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if i == x86.REG_SP {
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r, i = i, r
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}
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case ssa.Op386LEAL2:
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p.From.Scale = 2
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case ssa.Op386LEAL4:
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p.From.Scale = 4
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case ssa.Op386LEAL8:
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p.From.Scale = 8
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}
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = r
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p.From.Index = i
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.Op386LEAL:
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p := s.Prog(x86.ALEAL)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.Op386CMPL, ssa.Op386CMPW, ssa.Op386CMPB,
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ssa.Op386TESTL, ssa.Op386TESTW, ssa.Op386TESTB:
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opregreg(s, v.Op.Asm(), v.Args[1].Reg(), v.Args[0].Reg())
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case ssa.Op386UCOMISS, ssa.Op386UCOMISD:
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// Go assembler has swapped operands for UCOMISx relative to CMP,
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// must account for that right here.
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opregreg(s, v.Op.Asm(), v.Args[0].Reg(), v.Args[1].Reg())
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case ssa.Op386CMPLconst, ssa.Op386CMPWconst, ssa.Op386CMPBconst:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_CONST
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p.To.Offset = v.AuxInt
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case ssa.Op386TESTLconst, ssa.Op386TESTWconst, ssa.Op386TESTBconst:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Args[0].Reg()
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case ssa.Op386CMPLload, ssa.Op386CMPWload, ssa.Op386CMPBload:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Args[1].Reg()
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case ssa.Op386CMPLconstload, ssa.Op386CMPWconstload, ssa.Op386CMPBconstload:
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sc := v.AuxValAndOff()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux2(&p.From, v, sc.Off())
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p.To.Type = obj.TYPE_CONST
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p.To.Offset = sc.Val()
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case ssa.Op386MOVLconst:
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x := v.Reg()
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// If flags aren't live (indicated by v.Aux == nil),
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// then we can rewrite MOV $0, AX into XOR AX, AX.
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if v.AuxInt == 0 && v.Aux == nil {
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p := s.Prog(x86.AXORL)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = x
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break
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}
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = x
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case ssa.Op386MOVSSconst, ssa.Op386MOVSDconst:
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x := v.Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_FCONST
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p.From.Val = math.Float64frombits(uint64(v.AuxInt))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = x
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case ssa.Op386MOVSSconst1, ssa.Op386MOVSDconst1:
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p := s.Prog(x86.ALEAL)
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p.From.Type = obj.TYPE_MEM
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p.From.Name = obj.NAME_EXTERN
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f := math.Float64frombits(uint64(v.AuxInt))
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if v.Op == ssa.Op386MOVSDconst1 {
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p.From.Sym = gc.Ctxt.Float64Sym(f)
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} else {
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p.From.Sym = gc.Ctxt.Float32Sym(float32(f))
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}
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.Op386MOVSSconst2, ssa.Op386MOVSDconst2:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.Op386MOVSSload, ssa.Op386MOVSDload, ssa.Op386MOVLload, ssa.Op386MOVWload, ssa.Op386MOVBload, ssa.Op386MOVBLSXload, ssa.Op386MOVWLSXload:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.Op386MOVBloadidx1, ssa.Op386MOVWloadidx1, ssa.Op386MOVLloadidx1, ssa.Op386MOVSSloadidx1, ssa.Op386MOVSDloadidx1,
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ssa.Op386MOVSDloadidx8, ssa.Op386MOVLloadidx4, ssa.Op386MOVSSloadidx4, ssa.Op386MOVWloadidx2:
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r := v.Args[0].Reg()
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i := v.Args[1].Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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switch v.Op {
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case ssa.Op386MOVBloadidx1, ssa.Op386MOVWloadidx1, ssa.Op386MOVLloadidx1, ssa.Op386MOVSSloadidx1, ssa.Op386MOVSDloadidx1:
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if i == x86.REG_SP {
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r, i = i, r
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}
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p.From.Scale = 1
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case ssa.Op386MOVSDloadidx8:
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p.From.Scale = 8
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case ssa.Op386MOVLloadidx4, ssa.Op386MOVSSloadidx4:
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p.From.Scale = 4
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case ssa.Op386MOVWloadidx2:
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p.From.Scale = 2
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}
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p.From.Reg = r
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p.From.Index = i
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.Op386ADDLloadidx4, ssa.Op386SUBLloadidx4, ssa.Op386MULLloadidx4,
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ssa.Op386ANDLloadidx4, ssa.Op386ORLloadidx4, ssa.Op386XORLloadidx4:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[1].Reg()
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p.From.Index = v.Args[2].Reg()
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p.From.Scale = 4
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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if v.Reg() != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
|
case ssa.Op386ADDLload, ssa.Op386SUBLload, ssa.Op386MULLload,
|
ssa.Op386ANDLload, ssa.Op386ORLload, ssa.Op386XORLload,
|
ssa.Op386ADDSDload, ssa.Op386ADDSSload, ssa.Op386SUBSDload, ssa.Op386SUBSSload,
|
ssa.Op386MULSDload, ssa.Op386MULSSload, ssa.Op386DIVSSload, ssa.Op386DIVSDload:
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_MEM
|
p.From.Reg = v.Args[1].Reg()
|
gc.AddAux(&p.From, v)
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
if v.Reg() != v.Args[0].Reg() {
|
v.Fatalf("input[0] and output not in same register %s", v.LongString())
|
}
|
case ssa.Op386MOVSSstore, ssa.Op386MOVSDstore, ssa.Op386MOVLstore, ssa.Op386MOVWstore, ssa.Op386MOVBstore,
|
ssa.Op386ADDLmodify, ssa.Op386SUBLmodify, ssa.Op386ANDLmodify, ssa.Op386ORLmodify, ssa.Op386XORLmodify:
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = v.Args[1].Reg()
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = v.Args[0].Reg()
|
gc.AddAux(&p.To, v)
|
case ssa.Op386ADDLconstmodify:
|
sc := v.AuxValAndOff()
|
val := sc.Val()
|
if val == 1 || val == -1 {
|
var p *obj.Prog
|
if val == 1 {
|
p = s.Prog(x86.AINCL)
|
} else {
|
p = s.Prog(x86.ADECL)
|
}
|
off := sc.Off()
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = v.Args[0].Reg()
|
gc.AddAux2(&p.To, v, off)
|
break
|
}
|
fallthrough
|
case ssa.Op386ANDLconstmodify, ssa.Op386ORLconstmodify, ssa.Op386XORLconstmodify:
|
sc := v.AuxValAndOff()
|
off := sc.Off()
|
val := sc.Val()
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_CONST
|
p.From.Offset = val
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = v.Args[0].Reg()
|
gc.AddAux2(&p.To, v, off)
|
case ssa.Op386MOVBstoreidx1, ssa.Op386MOVWstoreidx1, ssa.Op386MOVLstoreidx1, ssa.Op386MOVSSstoreidx1, ssa.Op386MOVSDstoreidx1,
|
ssa.Op386MOVSDstoreidx8, ssa.Op386MOVSSstoreidx4, ssa.Op386MOVLstoreidx4, ssa.Op386MOVWstoreidx2,
|
ssa.Op386ADDLmodifyidx4, ssa.Op386SUBLmodifyidx4, ssa.Op386ANDLmodifyidx4, ssa.Op386ORLmodifyidx4, ssa.Op386XORLmodifyidx4:
|
r := v.Args[0].Reg()
|
i := v.Args[1].Reg()
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = v.Args[2].Reg()
|
p.To.Type = obj.TYPE_MEM
|
switch v.Op {
|
case ssa.Op386MOVBstoreidx1, ssa.Op386MOVWstoreidx1, ssa.Op386MOVLstoreidx1, ssa.Op386MOVSSstoreidx1, ssa.Op386MOVSDstoreidx1:
|
if i == x86.REG_SP {
|
r, i = i, r
|
}
|
p.To.Scale = 1
|
case ssa.Op386MOVSDstoreidx8:
|
p.To.Scale = 8
|
case ssa.Op386MOVSSstoreidx4, ssa.Op386MOVLstoreidx4,
|
ssa.Op386ADDLmodifyidx4, ssa.Op386SUBLmodifyidx4, ssa.Op386ANDLmodifyidx4, ssa.Op386ORLmodifyidx4, ssa.Op386XORLmodifyidx4:
|
p.To.Scale = 4
|
case ssa.Op386MOVWstoreidx2:
|
p.To.Scale = 2
|
}
|
p.To.Reg = r
|
p.To.Index = i
|
gc.AddAux(&p.To, v)
|
case ssa.Op386MOVLstoreconst, ssa.Op386MOVWstoreconst, ssa.Op386MOVBstoreconst:
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_CONST
|
sc := v.AuxValAndOff()
|
p.From.Offset = sc.Val()
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = v.Args[0].Reg()
|
gc.AddAux2(&p.To, v, sc.Off())
|
case ssa.Op386ADDLconstmodifyidx4:
|
sc := v.AuxValAndOff()
|
val := sc.Val()
|
if val == 1 || val == -1 {
|
var p *obj.Prog
|
if val == 1 {
|
p = s.Prog(x86.AINCL)
|
} else {
|
p = s.Prog(x86.ADECL)
|
}
|
off := sc.Off()
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = v.Args[0].Reg()
|
p.To.Scale = 4
|
p.To.Index = v.Args[1].Reg()
|
gc.AddAux2(&p.To, v, off)
|
break
|
}
|
fallthrough
|
case ssa.Op386MOVLstoreconstidx1, ssa.Op386MOVLstoreconstidx4, ssa.Op386MOVWstoreconstidx1, ssa.Op386MOVWstoreconstidx2, ssa.Op386MOVBstoreconstidx1,
|
ssa.Op386ANDLconstmodifyidx4, ssa.Op386ORLconstmodifyidx4, ssa.Op386XORLconstmodifyidx4:
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_CONST
|
sc := v.AuxValAndOff()
|
p.From.Offset = sc.Val()
|
r := v.Args[0].Reg()
|
i := v.Args[1].Reg()
|
switch v.Op {
|
case ssa.Op386MOVBstoreconstidx1, ssa.Op386MOVWstoreconstidx1, ssa.Op386MOVLstoreconstidx1:
|
p.To.Scale = 1
|
if i == x86.REG_SP {
|
r, i = i, r
|
}
|
case ssa.Op386MOVWstoreconstidx2:
|
p.To.Scale = 2
|
case ssa.Op386MOVLstoreconstidx4,
|
ssa.Op386ADDLconstmodifyidx4, ssa.Op386ANDLconstmodifyidx4, ssa.Op386ORLconstmodifyidx4, ssa.Op386XORLconstmodifyidx4:
|
p.To.Scale = 4
|
}
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = r
|
p.To.Index = i
|
gc.AddAux2(&p.To, v, sc.Off())
|
case ssa.Op386MOVWLSX, ssa.Op386MOVBLSX, ssa.Op386MOVWLZX, ssa.Op386MOVBLZX,
|
ssa.Op386CVTSL2SS, ssa.Op386CVTSL2SD,
|
ssa.Op386CVTTSS2SL, ssa.Op386CVTTSD2SL,
|
ssa.Op386CVTSS2SD, ssa.Op386CVTSD2SS:
|
opregreg(s, v.Op.Asm(), v.Reg(), v.Args[0].Reg())
|
case ssa.Op386DUFFZERO:
|
p := s.Prog(obj.ADUFFZERO)
|
p.To.Type = obj.TYPE_ADDR
|
p.To.Sym = gc.Duffzero
|
p.To.Offset = v.AuxInt
|
case ssa.Op386DUFFCOPY:
|
p := s.Prog(obj.ADUFFCOPY)
|
p.To.Type = obj.TYPE_ADDR
|
p.To.Sym = gc.Duffcopy
|
p.To.Offset = v.AuxInt
|
|
case ssa.OpCopy: // TODO: use MOVLreg for reg->reg copies instead of OpCopy?
|
if v.Type.IsMemory() {
|
return
|
}
|
x := v.Args[0].Reg()
|
y := v.Reg()
|
if x != y {
|
opregreg(s, moveByType(v.Type), y, x)
|
}
|
case ssa.OpLoadReg:
|
if v.Type.IsFlags() {
|
v.Fatalf("load flags not implemented: %v", v.LongString())
|
return
|
}
|
p := s.Prog(loadByType(v.Type))
|
gc.AddrAuto(&p.From, v.Args[0])
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
|
case ssa.OpStoreReg:
|
if v.Type.IsFlags() {
|
v.Fatalf("store flags not implemented: %v", v.LongString())
|
return
|
}
|
p := s.Prog(storeByType(v.Type))
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = v.Args[0].Reg()
|
gc.AddrAuto(&p.To, v)
|
case ssa.Op386LoweredGetClosurePtr:
|
// Closure pointer is DX.
|
gc.CheckLoweredGetClosurePtr(v)
|
case ssa.Op386LoweredGetG:
|
r := v.Reg()
|
// See the comments in cmd/internal/obj/x86/obj6.go
|
// near CanUse1InsnTLS for a detailed explanation of these instructions.
|
if x86.CanUse1InsnTLS(gc.Ctxt) {
|
// MOVL (TLS), r
|
p := s.Prog(x86.AMOVL)
|
p.From.Type = obj.TYPE_MEM
|
p.From.Reg = x86.REG_TLS
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = r
|
} else {
|
// MOVL TLS, r
|
// MOVL (r)(TLS*1), r
|
p := s.Prog(x86.AMOVL)
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = x86.REG_TLS
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = r
|
q := s.Prog(x86.AMOVL)
|
q.From.Type = obj.TYPE_MEM
|
q.From.Reg = r
|
q.From.Index = x86.REG_TLS
|
q.From.Scale = 1
|
q.To.Type = obj.TYPE_REG
|
q.To.Reg = r
|
}
|
|
case ssa.Op386LoweredGetCallerPC:
|
p := s.Prog(x86.AMOVL)
|
p.From.Type = obj.TYPE_MEM
|
p.From.Offset = -4 // PC is stored 4 bytes below first parameter.
|
p.From.Name = obj.NAME_PARAM
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
|
case ssa.Op386LoweredGetCallerSP:
|
// caller's SP is the address of the first arg
|
p := s.Prog(x86.AMOVL)
|
p.From.Type = obj.TYPE_ADDR
|
p.From.Offset = -gc.Ctxt.FixedFrameSize() // 0 on 386, just to be consistent with other architectures
|
p.From.Name = obj.NAME_PARAM
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
|
case ssa.Op386LoweredWB:
|
p := s.Prog(obj.ACALL)
|
p.To.Type = obj.TYPE_MEM
|
p.To.Name = obj.NAME_EXTERN
|
p.To.Sym = v.Aux.(*obj.LSym)
|
|
case ssa.Op386CALLstatic, ssa.Op386CALLclosure, ssa.Op386CALLinter:
|
s.Call(v)
|
case ssa.Op386NEGL,
|
ssa.Op386BSWAPL,
|
ssa.Op386NOTL:
|
r := v.Reg()
|
if r != v.Args[0].Reg() {
|
v.Fatalf("input[0] and output not in same register %s", v.LongString())
|
}
|
p := s.Prog(v.Op.Asm())
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = r
|
case ssa.Op386BSFL, ssa.Op386BSFW,
|
ssa.Op386BSRL, ssa.Op386BSRW,
|
ssa.Op386SQRTSD:
|
p := s.Prog(v.Op.Asm())
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = v.Args[0].Reg()
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
case ssa.Op386SETEQ, ssa.Op386SETNE,
|
ssa.Op386SETL, ssa.Op386SETLE,
|
ssa.Op386SETG, ssa.Op386SETGE,
|
ssa.Op386SETGF, ssa.Op386SETGEF,
|
ssa.Op386SETB, ssa.Op386SETBE,
|
ssa.Op386SETORD, ssa.Op386SETNAN,
|
ssa.Op386SETA, ssa.Op386SETAE,
|
ssa.Op386SETO:
|
p := s.Prog(v.Op.Asm())
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
|
case ssa.Op386SETNEF:
|
p := s.Prog(v.Op.Asm())
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
q := s.Prog(x86.ASETPS)
|
q.To.Type = obj.TYPE_REG
|
q.To.Reg = x86.REG_AX
|
opregreg(s, x86.AORL, v.Reg(), x86.REG_AX)
|
|
case ssa.Op386SETEQF:
|
p := s.Prog(v.Op.Asm())
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = v.Reg()
|
q := s.Prog(x86.ASETPC)
|
q.To.Type = obj.TYPE_REG
|
q.To.Reg = x86.REG_AX
|
opregreg(s, x86.AANDL, v.Reg(), x86.REG_AX)
|
|
case ssa.Op386InvertFlags:
|
v.Fatalf("InvertFlags should never make it to codegen %v", v.LongString())
|
case ssa.Op386FlagEQ, ssa.Op386FlagLT_ULT, ssa.Op386FlagLT_UGT, ssa.Op386FlagGT_ULT, ssa.Op386FlagGT_UGT:
|
v.Fatalf("Flag* ops should never make it to codegen %v", v.LongString())
|
case ssa.Op386REPSTOSL:
|
s.Prog(x86.AREP)
|
s.Prog(x86.ASTOSL)
|
case ssa.Op386REPMOVSL:
|
s.Prog(x86.AREP)
|
s.Prog(x86.AMOVSL)
|
case ssa.Op386LoweredNilCheck:
|
// Issue a load which will fault if the input is nil.
|
// TODO: We currently use the 2-byte instruction TESTB AX, (reg).
|
// Should we use the 3-byte TESTB $0, (reg) instead? It is larger
|
// but it doesn't have false dependency on AX.
|
// Or maybe allocate an output register and use MOVL (reg),reg2 ?
|
// That trades clobbering flags for clobbering a register.
|
p := s.Prog(x86.ATESTB)
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = x86.REG_AX
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = v.Args[0].Reg()
|
gc.AddAux(&p.To, v)
|
if gc.Debug_checknil != 0 && v.Pos.Line() > 1 { // v.Pos.Line()==1 in generated wrappers
|
gc.Warnl(v.Pos, "generated nil check")
|
}
|
case ssa.Op386FCHS:
|
v.Fatalf("FCHS in non-387 mode")
|
case ssa.OpClobber:
|
p := s.Prog(x86.AMOVL)
|
p.From.Type = obj.TYPE_CONST
|
p.From.Offset = 0xdeaddead
|
p.To.Type = obj.TYPE_MEM
|
p.To.Reg = x86.REG_SP
|
gc.AddAux(&p.To, v)
|
default:
|
v.Fatalf("genValue not implemented: %s", v.LongString())
|
}
|
}
|
|
var blockJump = [...]struct {
|
asm, invasm obj.As
|
}{
|
ssa.Block386EQ: {x86.AJEQ, x86.AJNE},
|
ssa.Block386NE: {x86.AJNE, x86.AJEQ},
|
ssa.Block386LT: {x86.AJLT, x86.AJGE},
|
ssa.Block386GE: {x86.AJGE, x86.AJLT},
|
ssa.Block386LE: {x86.AJLE, x86.AJGT},
|
ssa.Block386GT: {x86.AJGT, x86.AJLE},
|
ssa.Block386OS: {x86.AJOS, x86.AJOC},
|
ssa.Block386OC: {x86.AJOC, x86.AJOS},
|
ssa.Block386ULT: {x86.AJCS, x86.AJCC},
|
ssa.Block386UGE: {x86.AJCC, x86.AJCS},
|
ssa.Block386UGT: {x86.AJHI, x86.AJLS},
|
ssa.Block386ULE: {x86.AJLS, x86.AJHI},
|
ssa.Block386ORD: {x86.AJPC, x86.AJPS},
|
ssa.Block386NAN: {x86.AJPS, x86.AJPC},
|
}
|
|
var eqfJumps = [2][2]gc.FloatingEQNEJump{
|
{{Jump: x86.AJNE, Index: 1}, {Jump: x86.AJPS, Index: 1}}, // next == b.Succs[0]
|
{{Jump: x86.AJNE, Index: 1}, {Jump: x86.AJPC, Index: 0}}, // next == b.Succs[1]
|
}
|
var nefJumps = [2][2]gc.FloatingEQNEJump{
|
{{Jump: x86.AJNE, Index: 0}, {Jump: x86.AJPC, Index: 1}}, // next == b.Succs[0]
|
{{Jump: x86.AJNE, Index: 0}, {Jump: x86.AJPS, Index: 0}}, // next == b.Succs[1]
|
}
|
|
func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
|
switch b.Kind {
|
case ssa.BlockPlain:
|
if b.Succs[0].Block() != next {
|
p := s.Prog(obj.AJMP)
|
p.To.Type = obj.TYPE_BRANCH
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
}
|
case ssa.BlockDefer:
|
// defer returns in rax:
|
// 0 if we should continue executing
|
// 1 if we should jump to deferreturn call
|
p := s.Prog(x86.ATESTL)
|
p.From.Type = obj.TYPE_REG
|
p.From.Reg = x86.REG_AX
|
p.To.Type = obj.TYPE_REG
|
p.To.Reg = x86.REG_AX
|
p = s.Prog(x86.AJNE)
|
p.To.Type = obj.TYPE_BRANCH
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
|
if b.Succs[0].Block() != next {
|
p := s.Prog(obj.AJMP)
|
p.To.Type = obj.TYPE_BRANCH
|
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
}
|
case ssa.BlockExit:
|
s.Prog(obj.AUNDEF) // tell plive.go that we never reach here
|
case ssa.BlockRet:
|
s.Prog(obj.ARET)
|
case ssa.BlockRetJmp:
|
p := s.Prog(obj.AJMP)
|
p.To.Type = obj.TYPE_MEM
|
p.To.Name = obj.NAME_EXTERN
|
p.To.Sym = b.Aux.(*obj.LSym)
|
|
case ssa.Block386EQF:
|
s.FPJump(b, next, &eqfJumps)
|
|
case ssa.Block386NEF:
|
s.FPJump(b, next, &nefJumps)
|
|
case ssa.Block386EQ, ssa.Block386NE,
|
ssa.Block386LT, ssa.Block386GE,
|
ssa.Block386LE, ssa.Block386GT,
|
ssa.Block386OS, ssa.Block386OC,
|
ssa.Block386ULT, ssa.Block386UGT,
|
ssa.Block386ULE, ssa.Block386UGE:
|
jmp := blockJump[b.Kind]
|
switch next {
|
case b.Succs[0].Block():
|
s.Br(jmp.invasm, b.Succs[1].Block())
|
case b.Succs[1].Block():
|
s.Br(jmp.asm, b.Succs[0].Block())
|
default:
|
if b.Likely != ssa.BranchUnlikely {
|
s.Br(jmp.asm, b.Succs[0].Block())
|
s.Br(obj.AJMP, b.Succs[1].Block())
|
} else {
|
s.Br(jmp.invasm, b.Succs[1].Block())
|
s.Br(obj.AJMP, b.Succs[0].Block())
|
}
|
}
|
default:
|
b.Fatalf("branch not implemented: %s. Control: %s", b.LongString(), b.Control.LongString())
|
}
|
}
|
