/*
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* Allwinner sun8iw6p1 SoCs pinctrl driver.
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*
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* Copyright(c) 2016-2020 Allwinnertech Co., Ltd.
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* Author: WimHuang <huangwei@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun8iw6p1_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /*TX*/
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SUNXI_FUNCTION(0x3, "jtag0"), /*MS0*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /*RX*/
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SUNXI_FUNCTION(0x3, "jtag0"), /*CK0*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /*RTS*/
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SUNXI_FUNCTION(0x3, "jtag0"), /*DO0*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /*CTS*/
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SUNXI_FUNCTION(0x3, "jtag0"), /*DI0*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /*LRCK*/
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SUNXI_FUNCTION(0x3, "tdm0"), /*LRCK*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /*BCLK*/
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SUNXI_FUNCTION(0x3, "tdm0"), /*BCLK*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /*DOUT*/
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SUNXI_FUNCTION(0x3, "tdm0"), /*DOUT*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /*DIN*/
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SUNXI_FUNCTION(0x3, "tdm0"), /*DIN*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /*MCLK*/
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SUNXI_FUNCTION(0x3, "tdm0"), /*MCLK*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart0"), /*TX*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart0"), /*RX*/
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
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/*HOLE*/
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*WE*/
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SUNXI_FUNCTION(0x3, "spi0"), /*MOSI*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*ALE*/
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SUNXI_FUNCTION(0x3, "spi0"), /*MISO*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*CLE*/
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SUNXI_FUNCTION(0x3, "spi0"), /*CLK*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*CE1*/
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SUNXI_FUNCTION(0x3, "spi0"), /*CS*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*CE0*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*RE*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*CLK*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*RB0*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*CMD*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*RB1*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ0*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D0*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ1*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D1*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ2*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D2*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ3*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D3*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ4*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D4*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ5*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D5*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ6*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D6*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQ7*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*D7*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*DQS*/
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SUNXI_FUNCTION(0x3, "sdc2"), /*RST*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*CE2*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /*CE3*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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/*HOLE*/
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D2*/
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SUNXI_FUNCTION(0x4, "gmac0"), /**/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D3*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*grxd2*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D4*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*grxd1*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D5*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*grxd0*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D6*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*grxck*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D7*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*GRXCTL/ERXDV*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D10*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*GNULL/ERXERR*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D11*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD3*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D12*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD2*/
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SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D13*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D14*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD0*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D15*/
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SUNXI_FUNCTION(0x4, "gmac0"), /*GNULL/ECRS*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /*D18*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VP0*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GTXCK/ETXCK*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*D19*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VN0*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GTXCTL/ETXEN*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*D20*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VP1*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GNULL/ETXERR*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*D21*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VN1*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GCLKIN/ECOL*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*D22*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VP2*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GMDC*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*D23*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VN2*/
|
SUNXI_FUNCTION(0x4, "gmac0"), /*GMDIO*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*CLK*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VPC*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*DE*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VNC*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*HSYNC*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VP3*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd0"), /*VSYNC*/
|
SUNXI_FUNCTION(0x3, "lvds0"), /*VN3*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "pwm0"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
|
/*HOLE*/
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*PCLK*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*CLK*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*MCLK*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*DE*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*HSYNC*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*HSYNC*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*VSYNC*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*VSYNC*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D0*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D2*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D0*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D3*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D4*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D2*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D5*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D3*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D6*/
|
SUNXI_FUNCTION(0x3, "uart4"), /*TX*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D4*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D7*/
|
SUNXI_FUNCTION(0x3, "uart4"), /*RX*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D5*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D8*/
|
SUNXI_FUNCTION(0x3, "uart4"), /*RTS*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D6*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*D9*/
|
SUNXI_FUNCTION(0x3, "uart4"), /*CTS*/
|
SUNXI_FUNCTION(0x4, "ccir0"), /*D7*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*SCK*/
|
SUNXI_FUNCTION(0x3, "twi2"), /*SCK*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi0"), /*SDA*/
|
SUNXI_FUNCTION(0x3, "twi2"), /*SDA*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "spdif0"), /*DOUT*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
|
/*HOLE*/
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /*D1*/
|
SUNXI_FUNCTION(0x3, "jtag0"), /*MS1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /*D0*/
|
SUNXI_FUNCTION(0x3, "jtag0"), /*DI1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /*CLK*/
|
SUNXI_FUNCTION(0x3, "uart0"), /*TX*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /*CMD*/
|
SUNXI_FUNCTION(0x3, "jtag0"), /*DO1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /*D3*/
|
SUNXI_FUNCTION(0x3, "uart0"), /*RX*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /*D2*/
|
SUNXI_FUNCTION(0x3, "jtag0"), /*CK1*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
|
/*HOLE*/
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /*CLK*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /*CMD*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /*D0*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /*D1*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /*D2*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /*D3*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /*TX*/
|
SUNXI_FUNCTION(0x3, "spi1"), /*CS*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /*RX*/
|
SUNXI_FUNCTION(0x3, "spi1"), /*CLK*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /*RTS*/
|
SUNXI_FUNCTION(0x3, "spi1"), /*DOUT*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /*CTS*/
|
SUNXI_FUNCTION(0x3, "spi1"), /*DIN*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /*BCLK*/
|
SUNXI_FUNCTION(0x3, "uart3"), /*TX*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /*LRCK*/
|
SUNXI_FUNCTION(0x3, "uart3"), /*RX*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /*DOUT*/
|
SUNXI_FUNCTION(0x3, "uart3"), /*RTS*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /*DIN*/
|
SUNXI_FUNCTION(0x3, "uart3"), /*CTS*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
|
|
/*HOLE*/
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi0"), /*SCK*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi0"), /*SDA*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi1"), /*SCK*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi1"), /*SDA*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi2"), /*SCK*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi2"), /*SDA*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "hdmi"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "hdmi"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "hdmi"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x5, "Vdevice"), /* virtual */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x5, "Vdevice"), /* virtual */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
|
};
|
|
static const unsigned sun8iw6p1_irq_bank_base[] = {0, 0, 0};
|
|
static const struct sunxi_pinctrl_desc sun8iw6p1_pinctrl_data = {
|
.pins = sun8iw6p1_pins,
|
.npins = ARRAY_SIZE(sun8iw6p1_pins),
|
.pin_base = 0,
|
.irq_banks = 3,
|
.irq_bank_base = sun8iw6p1_irq_bank_base,
|
};
|
|
static int sun8iw6p1_pinctrl_probe(struct platform_device *pdev)
|
{
|
return sunxi_pinctrl_init(pdev, &sun8iw6p1_pinctrl_data);
|
}
|
|
static const struct of_device_id sun8iw6p1_pinctrl_match[] = {
|
{ .compatible = "allwinner,sun8iw6p1-pinctrl", },
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, sun8iw6p1_pinctrl_match);
|
|
static struct platform_driver sun8iw6p1_pinctrl_driver = {
|
.probe = sun8iw6p1_pinctrl_probe,
|
.driver = {
|
.name = "sun8iw6p1-pinctrl",
|
.owner = THIS_MODULE,
|
.of_match_table = sun8iw6p1_pinctrl_match,
|
},
|
};
|
|
static int __init sun8iw6p1_pio_init(void)
|
{
|
int ret;
|
|
ret = platform_driver_register(&sun8iw6p1_pinctrl_driver);
|
if (IS_ERR_VALUE(ret)) {
|
pr_err("register sun8iw6p1 pio controller failed\n");
|
return -EINVAL;
|
}
|
|
return 0;
|
}
|
postcore_initcall(sun8iw6p1_pio_init);
|
|
MODULE_AUTHOR("WimHuang<huangwei@allwinnertech.com>");
|
MODULE_DESCRIPTION("Allwinner sun8iw6p1 pio pinctrl driver");
|
MODULE_LICENSE("GPL");
|
