/*
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* Allwinner sun8iw18p1 SoCs pinctrl driver.
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*
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* Copyright(c) 2017-2020 Allwinnertech Co., Ltd.
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* Author: huangshuosheng <huangshuosheng@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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* */
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun8iw18p1_pins[] = {
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#if defined(CONFIG_FPGA_V7_PLATFORM)
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 28),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 29),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 30),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 31),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "rgmii"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled")),
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#endif
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/* HOLE */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* TX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* MS0 */
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SUNXI_FUNCTION(0x5, "mdc"),
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* RX */
|
SUNXI_FUNCTION(0x3, "pwm1"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* CK0 */
|
SUNXI_FUNCTION(0x5, "mdio"),
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
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SUNXI_FUNCTION(0x3, "pwm2"),
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SUNXI_FUNCTION(0x4, "jtag0"), /* DO0 */
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SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
|
SUNXI_FUNCTION(0x3, "pwm3"),
|
SUNXI_FUNCTION(0x4, "jtag0"), /* DI0 */
|
SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
|
SUNXI_FUNCTION(0x3, "pwm4"),
|
SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT */
|
SUNXI_FUNCTION(0x5, "i2s0"), /* DIN1 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
|
SUNXI_FUNCTION(0x3, "pwm5"),
|
SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT1 */
|
SUNXI_FUNCTION(0x5, "i2s0"), /* DIN0 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
|
#if defined(CONFIG_FPGA_V4_PLATFORM) || defined(CONFIG_FPGA_V7_PLATFORM)
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
|
SUNXI_FUNCTION(0x0, "spdif"),
|
SUNXI_FUNCTION(0x1, "spdif"),
|
SUNXI_FUNCTION(0x2, "spdif"),
|
SUNXI_FUNCTION(0x3, "spdif"),
|
SUNXI_FUNCTION(0x4, "spdif"),
|
SUNXI_FUNCTION(0x5, "spdif"),
|
SUNXI_FUNCTION(0x7, "spdif"), /* spdif */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spdif"), /* spdif mclk */
|
SUNXI_FUNCTION(0x7, "spdif"), /* spdif in */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
|
|
#else
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
|
SUNXI_FUNCTION(0x3, "pwm6"),
|
SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT2 */
|
SUNXI_FUNCTION(0x5, "i2s0"), /* DIN3 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
|
SUNXI_FUNCTION(0x3, "pwm7"),
|
SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT3 */
|
SUNXI_FUNCTION(0x5, "i2s0"), /* DIN2 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
|
#endif
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart0"), /* LRCK */
|
SUNXI_FUNCTION(0x3, "dmic"), /* DATA3 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart0"), /* BCLK */
|
SUNXI_FUNCTION(0x3, "dmic"), /* DATA2 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT0 */
|
SUNXI_FUNCTION(0x3, "dmic"), /* DATA1 */
|
SUNXI_FUNCTION(0x4, "i2s1"), /* DIN1 */
|
SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT1 */
|
SUNXI_FUNCTION(0x3, "dmic"), /* DATA0 */
|
SUNXI_FUNCTION(0x4, "i2s1"), /* DIN0 */
|
SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* MCLK */
|
SUNXI_FUNCTION(0x3, "dmic"), /* CLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "pwm8"),
|
SUNXI_FUNCTION(0x3, "ledc"), /* DO */
|
SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */
|
|
#if defined(CONFIG_FPGA_V4_PLATFORM) || defined(CONFIG_FPGA_V7_PLATFORM)
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 BCLK */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 BCLK */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 BCLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PB_EINT23 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 24),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 LRCLK */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 LRCLK */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 LRCLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PB_EINT23 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 25),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 DOUT0 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 DOUT0 */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 DOUT0 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PB_EINT25 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 26),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 DOUT1 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 DOUT1 */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 DOUT1 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PB_EINT26 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 27),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 DOUT2 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 DOUT2 */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 DOUT2 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PB_EINT27 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 28),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 DOUT3 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 DOUT3 */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 DOUT3 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 28)), /* PB_EINT28 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 29),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s0"), /* I2S0 MCLK */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* I2S1 MCLK */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* I2S2 MCLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 29)), /* PB_EINT29 */
|
|
#endif
|
/* HOLE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* DS */
|
SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* RST */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
|
SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
|
SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
|
SUNXI_FUNCTION(0x5, "bootsel1"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
|
SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
|
SUNXI_FUNCTION(0x5, "bootsel2"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* CLK */
|
SUNXI_FUNCTION(0x5, "bootsel3"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* CMD */
|
SUNXI_FUNCTION(0x5, "bootsel4"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
|
SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D3 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D4 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D0 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D5 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D1 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D6 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D2 */
|
SUNXI_FUNCTION(0x4, "spi0"), /* WP */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
|
SUNXI_FUNCTION(0x3, "sdc2"), /* D7 */
|
SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
|
#if defined(CONFIG_FPGA_V4_PLATFORM)
|
/* HOLE */
|
#else
|
|
/* HOLE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
|
SUNXI_FUNCTION(0x3, "ledc"), /* o */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD1 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
|
SUNXI_FUNCTION(0x3, "pwm8"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD0*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D4 */
|
SUNXI_FUNCTION(0x3, "pwm3"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD1 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
|
SUNXI_FUNCTION(0x3, "pwm4"),
|
SUNXI_FUNCTION(0x5, "regii"), /* RXD0 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
|
SUNXI_FUNCTION(0x3, "pwm5"),
|
SUNXI_FUNCTION(0x5, "EPHY"), /* 25M */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
|
SUNXI_FUNCTION(0x3, "pwm6"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXCTL */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
|
SUNXI_FUNCTION(0x3, "pwm0"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* CLKIN */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
|
SUNXI_FUNCTION(0x3, "pwm1"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXCK */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
|
SUNXI_FUNCTION(0x3, "pwm2"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXCTRL */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
|
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
|
SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD3 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
|
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
|
SUNXI_FUNCTION(0x4, "spdif"), /* IN */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD2 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
|
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
|
SUNXI_FUNCTION(0x4, "ledc"), /* D0 */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD3 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
|
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD2 */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
|
SUNXI_FUNCTION(0x3, "pwm7"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXCK */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
|
SUNXI_FUNCTION(0x4, "twi0"), /* SCK */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
|
SUNXI_FUNCTION(0x4, "twi0"), /* SDA */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
|
SUNXI_FUNCTION(0x4, "twi1"), /* SCK */
|
SUNXI_FUNCTION(0x5, "mdc"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
|
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
|
SUNXI_FUNCTION(0x4, "twi1"), /* SDA */
|
SUNXI_FUNCTION(0x5, "mdio"),
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
|
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
|
SUNXI_FUNCTION(0x3, "uart4"), /* RX*/
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */
|
SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
|
SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
|
SUNXI_FUNCTION(0x7, "io_disabled")),
|
#endif
|
/* HOLE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* MCLK */
|
SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD3 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PE_EINT0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
|
SUNXI_FUNCTION(0x3, "twi2"), /* SCK */
|
SUNXI_FUNCTION(0x4, "spdif"), /* IN */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD2 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PE_EINT1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "ledc"), /* OUT */
|
SUNXI_FUNCTION(0x3, "twi2"), /* SDA */
|
SUNXI_FUNCTION(0x4, "pwm8"),
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD1 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PE_EINT2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
|
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXD0 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PE_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
|
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* RXCK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PE_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT0 */
|
SUNXI_FUNCTION(0x3, "pll_lock_dbg"),
|
SUNXI_FUNCTION(0x4, "i2s1"), /* DIN1 */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* rxctrl */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PE_EINT5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT1 */
|
SUNXI_FUNCTION(0x3, "i2s1"), /* DIN0 */
|
SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
|
SUNXI_FUNCTION(0x5, "rgmii"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PE_EINT6 */
|
/* HOLE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /* D1 */
|
SUNXI_FUNCTION(0x3, "jtag0"), /* MS1 */
|
SUNXI_FUNCTION(0x5, "rgmii"), /*TXD3*/
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /* D0 */
|
SUNXI_FUNCTION(0x3, "jtag0"), /* DI1 */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD2 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /* CLK */
|
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD1 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /* CMD */
|
SUNXI_FUNCTION(0x3, "jtag0"), /* DO1 */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXD0 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /* D3 */
|
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
|
SUNXI_FUNCTION(0x5, "rgmii"), /* TXCK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc0"), /* D2 */
|
SUNXI_FUNCTION(0x3, "jtag0"), /* CK1 */
|
SUNXI_FUNCTION(0x5, "rgmii"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "ir_tx"),
|
SUNXI_FUNCTION(0x5, "ephy"), /* 25M */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
|
#if defined(CONFIG_FPGA_V4_PLATFORM) || defined(CONFIG_FPGA_V7_PLATFORM)
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "dmic"), /* DMIC_CLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
|
#endif
|
/* HOLE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /* CLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /* CMD */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /* D0 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /* D1 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "i2s2"), /* MCLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */
|
SUNXI_FUNCTION(0x3, "i2s2"), /* LRCK */
|
SUNXI_FUNCTION(0x5, "bist_result0"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */
|
SUNXI_FUNCTION(0x3, "i2s2"), /* BCLK */
|
SUNXI_FUNCTION(0x5, "bist_result1"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */
|
SUNXI_FUNCTION(0x3, "i2s2"), /* DOUT0 */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* DIN1 */
|
SUNXI_FUNCTION(0x5, "bist_result2"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "aif3"), /* DIN */
|
SUNXI_FUNCTION(0x3, "i2s2"), /* DOUT1 */
|
SUNXI_FUNCTION(0x4, "i2s2"), /* DIN0 */
|
SUNXI_FUNCTION(0x5, "bist_result3"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)),
|
|
|
/* HOLE */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi0"), /* SCK */
|
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
|
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi0"), /* SDA */
|
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
|
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi1"), /* SCK */
|
SUNXI_FUNCTION(0x3, "ledc"), /* DO */
|
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "twi1"), /* SDA */
|
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
|
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart3"), /* TX */
|
SUNXI_FUNCTION(0x3, "spi1"), /* CS */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart3"), /* RX */
|
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
|
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
|
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 7)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "ledc"), /* DO */
|
SUNXI_FUNCTION(0x3, "spdif"), /* IN */
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 8)),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "pwm8"),
|
SUNXI_FUNCTION(0x3, "ir_tx"),
|
SUNXI_FUNCTION(0x4, "cpu_cur_w"),
|
SUNXI_FUNCTION(0x7, "io_disabled"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 9)),
|
};
|
|
static const unsigned int sun8iw18p1_irq_bank_base[] = {
|
SUNXI_PIO_BANK_BASE(PB_BASE, 0),
|
SUNXI_PIO_BANK_BASE(PE_BASE, 1),
|
SUNXI_PIO_BANK_BASE(PF_BASE, 2),
|
SUNXI_PIO_BANK_BASE(PG_BASE, 3),
|
SUNXI_PIO_BANK_BASE(PH_BASE, 4),
|
};
|
|
static const struct sunxi_pinctrl_desc sun8iw18p1_pinctrl_data = {
|
.pins = sun8iw18p1_pins,
|
.npins = ARRAY_SIZE(sun8iw18p1_pins),
|
.pin_base = 0,
|
.irq_banks = 5,
|
.irq_bank_base = sun8iw18p1_irq_bank_base,
|
};
|
|
static int sun8iw18p1_pinctrl_probe(struct platform_device *pdev)
|
{
|
return sunxi_pinctrl_init(pdev, &sun8iw18p1_pinctrl_data);
|
}
|
|
static const struct of_device_id sun8iw18p1_pinctrl_match[] = {
|
{ .compatible = "allwinner,sun8iw18p1-pinctrl", },
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, sun8iw18p1_pinctrl_match);
|
|
static struct platform_driver sun8iw18p1_pinctrl_driver = {
|
.probe = sun8iw18p1_pinctrl_probe,
|
.driver = {
|
.name = "sun8iw18p1-pinctrl",
|
.owner = THIS_MODULE,
|
.of_match_table = sun8iw18p1_pinctrl_match,
|
},
|
};
|
|
static int __init sun8iw18p1_pio_init(void)
|
{
|
int ret;
|
|
ret = platform_driver_register(&sun8iw18p1_pinctrl_driver);
|
if (ret) {
|
pr_err("register sun8iw18p1 pio controller failed\n");
|
return -EINVAL;
|
}
|
return 0;
|
}
|
postcore_initcall(sun8iw18p1_pio_init);
|
|
MODULE_AUTHOR("huangshuosheng<huangshuosheng@allwinnertech.com>");
|
MODULE_DESCRIPTION("Allwinner sun8iw18p1 pio pinctrl driver");
|
MODULE_LICENSE("GPL");
|
