/******************************************************************************
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*
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* Copyright (C) 2019-2021 Aicsemi Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************/
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#ifndef HARDWARE_H
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#define HARDWARE_H
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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#define cpu_to_le16(d) (d)
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#define cpu_to_le32(d) (d)
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#define le16_to_cpu(d) (d)
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#define le32_to_cpu(d) (d)
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#elif __BYTE_ORDER == __BIG_ENDIAN
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#define cpu_to_le16(d) bswap_16(d)
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#define cpu_to_le32(d) bswap_32(d)
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#define le16_to_cpu(d) bswap_16(d)
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#define le32_to_cpu(d) bswap_32(d)
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#else
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#error "Unknown byte order"
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#endif
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#define HCI_CMD_MAX_LEN 258
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#define HCI_VERSION_MASK_10 (1<<0) //Bluetooth Core Spec 1.0b
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#define HCI_VERSION_MASK_11 (1<<1) //Bluetooth Core Spec 1.1
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#define HCI_VERSION_MASK_12 (1<<2) //Bluetooth Core Spec 1.2
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#define HCI_VERSION_MASK_20 (1<<3) //Bluetooth Core Spec 2.0+EDR
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#define HCI_VERSION_MASK_21 (1<<4) //Bluetooth Core Spec 2.1+EDR
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#define HCI_VERSION_MASK_30 (1<<5) //Bluetooth Core Spec 3.0+HS
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#define HCI_VERSION_MASK_40 (1<<6) //Bluetooth Core Spec 4.0
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#define HCI_VERSION_MASK_41 (1<<7) //Bluetooth Core Spec 4.1
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#define HCI_VERSION_MASK_42 (1<<8) //Bluetooth Core Spec 4.2
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#define HCI_VERSION_MASK_ALL (0xFFFFFFFF)
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#define HCI_EVT_CMD_CMPL_OPCODE_OFFSET (3) //opcode's offset in COMMAND Completed Event
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#define HCI_EVT_CMD_CMPL_STATUS_OFFSET (5) //status's offset in COMMAND Completed Event
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#define HCI_CMD_PREAMBLE_SIZE (3)
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#define HCI_CMD_READ_CHIP_TYPE_SIZE (5)
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#define H5_SYNC_REQ_SIZE (2)
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#define H5_SYNC_RESP_SIZE (2)
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#define H5_CONF_REQ_SIZE (3)
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#define H5_CONF_RESP_SIZE (2)
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#define AICBT_CONFIG_ID_VX_SET 0x01
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#define AICBT_CONFIG_ID_PTA_EN 0x0B
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/******************************************************************************
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** Local type definitions
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******************************************************************************/
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/* Hardware Configuration State */
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enum {
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HW_CFG_H5_INIT = 1,
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HW_CFG_READ_LOCAL_VER,
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HW_CFG_READ_ECO_VER, //eco version
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HW_CFG_READ_CHIP_TYPE,
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HW_CFG_START,
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HW_CFG_SET_UART_BAUD_HOST,//change FW baudrate
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HW_CFG_SET_UART_BAUD_CONTROLLER,//change Host baudrate
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HW_CFG_SET_UART_HW_FLOW_CONTROL,
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HW_CFG_RESET_CHANNEL_CONTROLLER,
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HW_RESET_CONTROLLER,
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HARDWARE_INIT_COMPLETE,
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HW_CFG_DL_FW_PATCH,
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HW_CFG_SET_BD_ADDR,
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#if (USE_CONTROLLER_BDADDR == TRUE)
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HW_CFG_READ_BD_ADDR,
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#endif
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HW_CFG_WR_RF_MDM_REGS,
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HW_CFG_WR_RF_MDM_REGS_END,
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HW_CFG_SET_RF_MODE,
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HW_CFG_RF_CALIB_REQ,
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HW_CFG_UPDATE_CONFIG_INFO,
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HW_CFG_WR_AON_PARAM,
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HW_CFG_SET_LP_LEVEL,
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HW_CFG_SET_PWR_CTRL_SLAVE,
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HW_CFG_SET_CPU_POWR_OFF_EN,
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};
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/* h/w config control block */
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typedef struct {
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uint8_t state; /* Hardware configuration state */
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int fw_fd; /* FW patch file fd */
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uint8_t f_set_baud_2; /* Baud rate switch state */
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char local_chip_name[LOCAL_NAME_BUFFER_LEN];
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} bt_hw_cfg_cb_t;
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/* low power mode parameters */
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typedef struct
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{
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uint8_t sleep_mode; /* 0(disable),1(UART),9(H5) */
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uint8_t host_stack_idle_threshold; /* Unit scale 300ms/25ms */
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uint8_t host_controller_idle_threshold; /* Unit scale 300ms/25ms */
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uint8_t bt_wake_polarity; /* 0=Active Low, 1= Active High */
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uint8_t host_wake_polarity; /* 0=Active Low, 1= Active High */
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uint8_t allow_host_sleep_during_sco;
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uint8_t combine_sleep_mode_and_lpm;
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uint8_t enable_uart_txd_tri_state; /* UART_TXD Tri-State */
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uint8_t sleep_guard_time; /* sleep guard time in 12.5ms */
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uint8_t wakeup_guard_time; /* wakeup guard time in 12.5ms */
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uint8_t txd_config; /* TXD is high in sleep state */
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uint8_t pulsed_host_wake; /* pulsed host wake if mode = 1 */
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} bt_lpm_param_t;
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struct aicbt_pta_config {
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///pta enable
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uint8_t pta_en;
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///pta sw enable
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uint8_t pta_sw_en;
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///pta hw enable
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uint8_t pta_hw_en;
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///pta method now using, 1:hw; 0:sw
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uint8_t pta_method;
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///pta bt grant duration
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uint16_t pta_bt_du;
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///pta wf grant duration
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uint16_t pta_wf_du;
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///pta bt grant duration sco
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uint16_t pta_bt_du_sco;
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///pta wf grant duration sco
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uint16_t pta_wf_du_sco;
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///pta bt grant duration esco
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uint16_t pta_bt_du_esco;
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///pta wf grant duration esco
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uint16_t pta_wf_du_esco;
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///pta bt grant duration for page
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uint16_t pta_bt_page_du;
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///pta acl cps value
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uint16_t pta_acl_cps_value;
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///pta sco cps value
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uint16_t pta_sco_cps_value;
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};
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struct hci_wr_rf_mdm_regs_cmd {
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uint16_t offset;
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uint8_t rcvd;
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uint8_t len;
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uint8_t data[248];
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};
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typedef enum {
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AIC_RF_MODE_NULL = 0x00,
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AIC_RF_MODE_BT_ONLY,
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AIC_RF_MODE_BT_COMBO,
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AIC_RF_MODE_BTWIFI_COMBO,
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AIC_RF_MODE_MAX,
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} aicbt_rf_mode;
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struct hci_set_rf_mode_cmd {
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uint8_t rf_mode;
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};
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struct buf_tag {
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uint8_t length;
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uint8_t data[128];
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};
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struct hci_rf_calib_req_cmd {
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uint8_t calib_type;
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uint16_t offset;
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struct buf_tag buff;
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};
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struct hci_vs_update_config_info_cmd {
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uint16_t config_id;
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uint16_t config_len;
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uint8_t config_data[32];
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};
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enum vs_update_config_info_state {
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VS_UPDATE_CONFIG_INFO_STATE_IDLE,
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VS_UPDATE_CONFIG_INFO_STATE_PTA_EN,
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VS_UPDATE_CONFIG_INFO_STATE_END,
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};
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extern uint32_t aicbt_up_config_info_state;
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extern uint32_t rf_mdm_table_index;
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extern aicbt_rf_mode bt_rf_mode;
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extern bool bt_rf_need_config;
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extern bool bt_rf_need_calib;
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extern uint32_t rf_mdm_regs_offset;
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extern const uint32_t rf_mdm_regs_table_bt_only[37][2];
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extern const uint32_t rf_mdm_regs_table_bt_combo[20][2];
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extern const struct aicbt_pta_config pta_config;
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extern struct hci_rf_calib_req_cmd rf_calib_req_bt_only;
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extern struct hci_rf_calib_req_cmd rf_calib_req_bt_combo;
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extern bt_hw_cfg_cb_t hw_cfg_cb;
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extern uint8_t vnd_local_bd_addr[BD_ADDR_LEN];
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aicbt_rf_mode hw_get_bt_rf_mode(void);
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bool hw_wr_rf_mdm_regs(HC_BT_HDR *p_buf);
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uint8_t hw_config_set_bdaddr(HC_BT_HDR *p_buf);
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bool hw_aic_bt_pta_en(HC_BT_HDR *p_buf);
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bool hw_set_rf_mode(HC_BT_HDR *p_buf);
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bool hw_rf_calib_req(HC_BT_HDR *p_buf);
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void hw_sco_config(void);
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int hw_set_audio_state(bt_vendor_op_audio_state_t *p_state);
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void hw_bt_assert_notify(void *p_mem);
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// uart only
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void hw_lpm_set_wake_state(uint8_t wake_assert);
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uint32_t hw_lpm_get_idle_timeout(void);
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#endif
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