.text
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/*
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* The head of l-loader is defined in below.
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* struct l_loader_head {
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* unsigned int first_instr;
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* unsigned char magic[16]; @ BOOTMAGICNUMBER!
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* unsigned int l_loader_start;
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* unsigned int l_loader_end;
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* };
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*/
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#define CPU0_CTRL_OFFSET 0x100
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#define CPU7_CTRL_OFFSET 0x800
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#define CPU0_RVBARADDR_OFFSET 0x158
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#define CPU7_RVBARADDR_OFFSET 0x858
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#define CPU_CTRL_AARCH64_MODE (1 << 7)
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#define SC_PERIPH_CLKEN3 0x230
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#define SC_PERIPH_RSTDIS3 0x334
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.global _start
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_start:
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b reset
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@ Android magic number: "BOOTMAGICNUMBER!"
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android_magic:
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.word 0x544f4f42
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.word 0x4947414d
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.word 0x4d554e43
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.word 0x21524542
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.word LLOADER_START @ LLOADER_START in RAM
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.word 0 @ LLOADER_END in RAM
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entries:
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@ 5 entries with 7 words
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.space 140
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.align 7
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reset:
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ldr r8, =(0xf9800000 + 0x700)
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str r0, [r8] @ download mode (1:usb,2:uart,0:boot)
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ldr r4, =0xf6504000 @ ACPU_CTRL register base
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@ set RVBAR for cpu0
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ldr r5, =CPU0_RVBARADDR_OFFSET
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ldr r6, =LLOADER_BL1_BIN
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mov r6, r6, lsr #2
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str r6, [r4, r5]
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1:
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ldr r0, [r4, r5]
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cmp r0, r6
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bne 1b
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mov r5, #CPU0_CTRL_OFFSET
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mov r6, #CPU7_CTRL_OFFSET
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2:
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ldr r0, [r4, r5] @ Load ACPU_SC_CPUx_CTRL
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orr r0, r0, #CPU_CTRL_AARCH64_MODE
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str r0, [r4, r5] @ Save to ACPU_SC_CPUx_CTRL
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ldr r0, [r4, r5]
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add r5, r5, #0x100 @ Iterate ACPU_SC_CPUx_CTRL
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cmp r5, r6
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ble 2b
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/*
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* Prepare UART2 & UART3 without baud rate initialization.
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* So always output on UART0 in l-loader.
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*/
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ldr r4, =0xf70100e0 @ UART2_RXD IOMG register
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mov r0, #0
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str r0, [r4]
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str r0, [r4, #4] @ UART2_TXD IOMG register
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ldr r0, [r4]
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ldr r4, =0xf7010188 @ UART3_RXD IOMG register
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mov r0, #1
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str r0, [r4]
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str r0, [r4, #4] @ UART3_TXD IOMG register
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ldr r1, [r4]
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ldr r4, =0xf7030000 @ PERI_CTRL register base
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@ By default, CLK_TXCO is the parent of CLK_UART3 in SC_CLK_SEL0
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ldr r5, =SC_PERIPH_RSTDIS3 @ unreset
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ldr r6, =SC_PERIPH_CLKEN3 @ enable PCLK
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mov r0, #(3 << 6) @ bit'6' & bit'7' (UART2 & UART3)
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str r0, [r4, r5]
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str r0, [r4, r6]
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@ execute warm reset to switch aarch64
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mov r2, #3
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mcr p15, 0, r2, c12, c0, 2
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wfi
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panic:
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b panic
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str_aarch64:
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.asciz "\nSwitch to aarch64 mode. CPU0 executes at 0x"
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