/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "calling_convention_mips.h"
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#include <android-base/logging.h>
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#include "arch/instruction_set.h"
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#include "handle_scope-inl.h"
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#include "utils/mips/managed_register_mips.h"
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namespace art {
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namespace mips {
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//
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// JNI calling convention constants.
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//
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// Up to how many float-like (float, double) args can be enregistered in floating-point registers.
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// The rest of the args must go in integer registers or on the stack.
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constexpr size_t kMaxFloatOrDoubleRegisterArguments = 2u;
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// Up to how many integer-like (pointers, objects, longs, int, short, bool, etc) args can be
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// enregistered. The rest of the args must go on the stack.
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constexpr size_t kMaxIntLikeRegisterArguments = 4u;
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static const Register kJniCoreArgumentRegisters[] = { A0, A1, A2, A3 };
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static const FRegister kJniFArgumentRegisters[] = { F12, F14 };
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static const DRegister kJniDArgumentRegisters[] = { D6, D7 };
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//
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// Managed calling convention constants.
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//
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static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
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static const FRegister kManagedFArgumentRegisters[] = { F8, F10, F12, F14, F16, F18 };
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static const DRegister kManagedDArgumentRegisters[] = { D4, D5, D6, D7, D8, D9 };
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static constexpr ManagedRegister kCalleeSaveRegisters[] = {
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// Core registers.
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MipsManagedRegister::FromCoreRegister(S2),
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MipsManagedRegister::FromCoreRegister(S3),
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MipsManagedRegister::FromCoreRegister(S4),
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MipsManagedRegister::FromCoreRegister(S5),
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MipsManagedRegister::FromCoreRegister(S6),
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MipsManagedRegister::FromCoreRegister(S7),
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MipsManagedRegister::FromCoreRegister(FP),
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// No hard float callee saves.
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};
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static constexpr uint32_t CalculateCoreCalleeSpillMask() {
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// RA is a special callee save which is not reported by CalleeSaveRegisters().
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uint32_t result = 1 << RA;
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for (auto&& r : kCalleeSaveRegisters) {
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if (r.AsMips().IsCoreRegister()) {
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result |= (1 << r.AsMips().AsCoreRegister());
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}
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}
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return result;
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}
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static constexpr uint32_t kCoreCalleeSpillMask = CalculateCoreCalleeSpillMask();
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static constexpr uint32_t kFpCalleeSpillMask = 0u;
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// Calling convention
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ManagedRegister MipsManagedRuntimeCallingConvention::InterproceduralScratchRegister() {
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return MipsManagedRegister::FromCoreRegister(T9);
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}
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ManagedRegister MipsJniCallingConvention::InterproceduralScratchRegister() {
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return MipsManagedRegister::FromCoreRegister(T9);
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}
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static ManagedRegister ReturnRegisterForShorty(const char* shorty) {
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if (shorty[0] == 'F') {
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return MipsManagedRegister::FromFRegister(F0);
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} else if (shorty[0] == 'D') {
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return MipsManagedRegister::FromDRegister(D0);
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} else if (shorty[0] == 'J') {
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return MipsManagedRegister::FromRegisterPair(V0_V1);
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} else if (shorty[0] == 'V') {
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return MipsManagedRegister::NoRegister();
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} else {
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return MipsManagedRegister::FromCoreRegister(V0);
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}
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}
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ManagedRegister MipsManagedRuntimeCallingConvention::ReturnRegister() {
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return ReturnRegisterForShorty(GetShorty());
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}
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ManagedRegister MipsJniCallingConvention::ReturnRegister() {
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return ReturnRegisterForShorty(GetShorty());
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}
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ManagedRegister MipsJniCallingConvention::IntReturnRegister() {
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return MipsManagedRegister::FromCoreRegister(V0);
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}
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// Managed runtime calling convention
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ManagedRegister MipsManagedRuntimeCallingConvention::MethodRegister() {
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return MipsManagedRegister::FromCoreRegister(A0);
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}
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bool MipsManagedRuntimeCallingConvention::IsCurrentParamInRegister() {
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return false; // Everything moved to stack on entry.
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}
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bool MipsManagedRuntimeCallingConvention::IsCurrentParamOnStack() {
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return true;
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}
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ManagedRegister MipsManagedRuntimeCallingConvention::CurrentParamRegister() {
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LOG(FATAL) << "Should not reach here";
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UNREACHABLE();
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}
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FrameOffset MipsManagedRuntimeCallingConvention::CurrentParamStackOffset() {
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CHECK(IsCurrentParamOnStack());
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FrameOffset result =
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FrameOffset(displacement_.Int32Value() + // displacement
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kFramePointerSize + // Method*
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(itr_slots_ * kFramePointerSize)); // offset into in args
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return result;
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}
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const ManagedRegisterEntrySpills& MipsManagedRuntimeCallingConvention::EntrySpills() {
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// We spill the argument registers on MIPS to free them up for scratch use, we then assume
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// all arguments are on the stack.
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if ((entry_spills_.size() == 0) && (NumArgs() > 0)) {
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uint32_t gpr_index = 1; // Skip A0, it is used for ArtMethod*.
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uint32_t fpr_index = 0;
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for (ResetIterator(FrameOffset(0)); HasNext(); Next()) {
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if (IsCurrentParamAFloatOrDouble()) {
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if (IsCurrentParamADouble()) {
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if (fpr_index < arraysize(kManagedDArgumentRegisters)) {
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entry_spills_.push_back(
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MipsManagedRegister::FromDRegister(kManagedDArgumentRegisters[fpr_index++]));
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} else {
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entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
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}
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} else {
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if (fpr_index < arraysize(kManagedFArgumentRegisters)) {
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entry_spills_.push_back(
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MipsManagedRegister::FromFRegister(kManagedFArgumentRegisters[fpr_index++]));
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} else {
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entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
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}
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}
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} else {
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if (IsCurrentParamALong() && !IsCurrentParamAReference()) {
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if (gpr_index == 1 || gpr_index == 3) {
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// Don't use A1-A2(A3-T0) as a register pair, move to A2-A3(T0-T1) instead.
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gpr_index++;
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}
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if (gpr_index < arraysize(kManagedCoreArgumentRegisters) - 1) {
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entry_spills_.push_back(
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MipsManagedRegister::FromCoreRegister(kManagedCoreArgumentRegisters[gpr_index++]));
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} else if (gpr_index == arraysize(kManagedCoreArgumentRegisters) - 1) {
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gpr_index++;
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entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
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} else {
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entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
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}
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}
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if (gpr_index < arraysize(kManagedCoreArgumentRegisters)) {
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entry_spills_.push_back(
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MipsManagedRegister::FromCoreRegister(kManagedCoreArgumentRegisters[gpr_index++]));
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} else {
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entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
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}
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}
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}
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}
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return entry_spills_;
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}
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// JNI calling convention
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MipsJniCallingConvention::MipsJniCallingConvention(bool is_static,
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bool is_synchronized,
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bool is_critical_native,
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const char* shorty)
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: JniCallingConvention(is_static,
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is_synchronized,
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is_critical_native,
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shorty,
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kMipsPointerSize) {
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// SYSTEM V - Application Binary Interface (MIPS RISC Processor):
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// Data Representation - Fundamental Types (3-4) specifies fundamental alignments for each type.
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// "Each member is assigned to the lowest available offset with the appropriate alignment. This
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// may require internal padding, depending on the previous member."
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//
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// All of our stack arguments are usually 4-byte aligned, however longs and doubles must be 8
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// bytes aligned. Add padding to maintain 8-byte alignment invariant.
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//
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// Compute padding to ensure longs and doubles are not split in o32.
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size_t padding = 0;
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size_t cur_arg, cur_reg;
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if (LIKELY(HasExtraArgumentsForJni())) {
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// Ignore the 'this' jobject or jclass for static methods and the JNIEnv.
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// We start at the aligned register A2.
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//
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// Ignore the first 2 parameters because they are guaranteed to be aligned.
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cur_arg = NumImplicitArgs(); // Skip the "this" argument.
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cur_reg = 2; // Skip {A0=JNIEnv, A1=jobject} / {A0=JNIEnv, A1=jclass} parameters (start at A2).
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} else {
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// Check every parameter.
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cur_arg = 0;
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cur_reg = 0;
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}
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// Shift across a logical register mapping that looks like:
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//
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// | A0 | A1 | A2 | A3 | SP+16 | SP+20 | SP+24 | ... | SP+n | SP+n+4 |
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//
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// or some of variants with floating-point registers (F12 and F14), for example
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//
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// | F12 | F14 | A3 | SP+16 | SP+20 | SP+24 | ... | SP+n | SP+n+4 |
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//
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// (where SP is the stack pointer at the start of called function).
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//
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// Any time there would normally be a long/double in an odd logical register,
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// we have to push out the rest of the mappings by 4 bytes to maintain an 8-byte alignment.
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//
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// This works for both physical register pairs {A0, A1}, {A2, A3},
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// floating-point registers F12, F14 and for when the value is on the stack.
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//
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// For example:
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// (a) long would normally go into A1, but we shift it into A2
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// | INT | (PAD) | LONG |
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// | A0 | A1 | A2 | A3 |
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//
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// (b) long would normally go into A3, but we shift it into SP
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// | INT | INT | INT | (PAD) | LONG |
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// | A0 | A1 | A2 | A3 | SP+16 SP+20 |
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//
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// where INT is any <=4 byte arg, and LONG is any 8-byte arg.
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for (; cur_arg < NumArgs(); cur_arg++) {
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if (IsParamALongOrDouble(cur_arg)) {
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if ((cur_reg & 1) != 0) {
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padding += 4;
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cur_reg++; // Additional bump to ensure alignment.
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}
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cur_reg += 2; // Bump the iterator twice for every long argument.
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} else {
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cur_reg++; // Bump the iterator for every argument.
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}
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}
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if (cur_reg < kMaxIntLikeRegisterArguments) {
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// As a special case when, as a result of shifting (or not) there are no arguments on the stack,
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// we actually have 0 stack padding.
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//
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// For example with @CriticalNative and:
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// (int, long) -> shifts the long but doesn't need to pad the stack
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//
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// shift
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// \/
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// | INT | (PAD) | LONG | (EMPTY) ...
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// | r0 | r1 | r2 | r3 | SP ...
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// /\
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// no stack padding
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padding_ = 0;
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} else {
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padding_ = padding;
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}
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// Argument Passing (3-17):
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// "When the first argument is integral, the remaining arguments are passed in the integer
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// registers."
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//
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// "The rules that determine which arguments go into registers and which ones must be passed on
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// the stack are most easily explained by considering the list of arguments as a structure,
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// aligned according to normal structure rules. Mapping of this structure into the combination of
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// stack and registers is as follows: up to two leading floating-point arguments can be passed in
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// $f12 and $f14; everything else with a structure offset greater than or equal to 16 is passed on
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// the stack. The remainder of the arguments are passed in $4..$7 based on their structure offset.
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// Holes left in the structure for alignment are unused, whether in registers or in the stack."
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//
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// For example with @CriticalNative and:
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// (a) first argument is not floating-point, so all go into integer registers
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// | INT | FLOAT | DOUBLE |
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// | A0 | A1 | A2 | A3 |
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// (b) first argument is floating-point, but 2nd is integer
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// | FLOAT | INT | DOUBLE |
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// | F12 | A1 | A2 | A3 |
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// (c) first two arguments are floating-point (float, double)
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// | FLOAT | (PAD) | DOUBLE | INT |
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// | F12 | | F14 | SP+16 |
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// (d) first two arguments are floating-point (double, float)
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// | DOUBLE | FLOAT | INT |
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// | F12 | F14 | A3 |
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// (e) first three arguments are floating-point, but just first two will go into fp registers
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// | DOUBLE | FLOAT | FLOAT |
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// | F12 | F14 | A3 |
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//
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// Find out if the first argument is a floating-point. In that case, floating-point registers will
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// be used for up to two leading floating-point arguments. Otherwise, all arguments will be passed
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// using integer registers.
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use_fp_arg_registers_ = false;
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if (is_critical_native) {
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if (NumArgs() > 0) {
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if (IsParamAFloatOrDouble(0)) {
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use_fp_arg_registers_ = true;
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}
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}
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}
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}
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uint32_t MipsJniCallingConvention::CoreSpillMask() const {
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return kCoreCalleeSpillMask;
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}
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uint32_t MipsJniCallingConvention::FpSpillMask() const {
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return kFpCalleeSpillMask;
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}
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ManagedRegister MipsJniCallingConvention::ReturnScratchRegister() const {
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return MipsManagedRegister::FromCoreRegister(AT);
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}
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size_t MipsJniCallingConvention::FrameSize() {
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// ArtMethod*, RA and callee save area size, local reference segment state.
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const size_t method_ptr_size = static_cast<size_t>(kMipsPointerSize);
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const size_t ra_return_addr_size = kFramePointerSize;
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const size_t callee_save_area_size = CalleeSaveRegisters().size() * kFramePointerSize;
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size_t frame_data_size = method_ptr_size + ra_return_addr_size + callee_save_area_size;
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if (LIKELY(HasLocalReferenceSegmentState())) {
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// Local reference segment state.
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frame_data_size += kFramePointerSize;
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}
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// References plus 2 words for HandleScope header.
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const size_t handle_scope_size = HandleScope::SizeOf(kMipsPointerSize, ReferenceCount());
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size_t total_size = frame_data_size;
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if (LIKELY(HasHandleScope())) {
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// HandleScope is sometimes excluded.
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total_size += handle_scope_size; // Handle scope size.
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}
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// Plus return value spill area size.
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total_size += SizeOfReturnValue();
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return RoundUp(total_size, kStackAlignment);
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}
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size_t MipsJniCallingConvention::OutArgSize() {
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// Argument Passing (3-17):
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// "Despite the fact that some or all of the arguments to a function are passed in registers,
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// always allocate space on the stack for all arguments. This stack space should be a structure
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// large enough to contain all the arguments, aligned according to normal structure rules (after
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// promotion and structure return pointer insertion). The locations within the stack frame used
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// for arguments are called the home locations."
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//
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// Allocate 16 bytes for home locations + space needed for stack arguments.
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return RoundUp(
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(kMaxIntLikeRegisterArguments + NumberOfOutgoingStackArgs()) * kFramePointerSize + padding_,
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kStackAlignment);
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}
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ArrayRef<const ManagedRegister> MipsJniCallingConvention::CalleeSaveRegisters() const {
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return ArrayRef<const ManagedRegister>(kCalleeSaveRegisters);
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}
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// JniCallingConvention ABI follows o32 where longs and doubles must occur
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// in even register numbers and stack slots.
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void MipsJniCallingConvention::Next() {
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JniCallingConvention::Next();
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if (LIKELY(HasNext())) { // Avoid CHECK failure for IsCurrentParam
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// Ensure slot is 8-byte aligned for longs/doubles (o32).
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if (IsCurrentParamALongOrDouble() && ((itr_slots_ & 0x1u) != 0)) {
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// itr_slots_ needs to be an even number, according to o32.
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itr_slots_++;
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}
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}
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}
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bool MipsJniCallingConvention::IsCurrentParamInRegister() {
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// Argument Passing (3-17):
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// "The rules that determine which arguments go into registers and which ones must be passed on
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// the stack are most easily explained by considering the list of arguments as a structure,
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// aligned according to normal structure rules. Mapping of this structure into the combination of
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// stack and registers is as follows: up to two leading floating-point arguments can be passed in
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// $f12 and $f14; everything else with a structure offset greater than or equal to 16 is passed on
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// the stack. The remainder of the arguments are passed in $4..$7 based on their structure offset.
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// Holes left in the structure for alignment are unused, whether in registers or in the stack."
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//
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// Even when floating-point registers are used, there can be up to 4 arguments passed in
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// registers.
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return itr_slots_ < kMaxIntLikeRegisterArguments;
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}
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bool MipsJniCallingConvention::IsCurrentParamOnStack() {
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return !IsCurrentParamInRegister();
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}
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ManagedRegister MipsJniCallingConvention::CurrentParamRegister() {
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CHECK_LT(itr_slots_, kMaxIntLikeRegisterArguments);
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// Up to two leading floating-point arguments can be passed in floating-point registers.
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if (use_fp_arg_registers_ && (itr_args_ < kMaxFloatOrDoubleRegisterArguments)) {
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if (IsCurrentParamAFloatOrDouble()) {
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if (IsCurrentParamADouble()) {
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return MipsManagedRegister::FromDRegister(kJniDArgumentRegisters[itr_args_]);
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} else {
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return MipsManagedRegister::FromFRegister(kJniFArgumentRegisters[itr_args_]);
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}
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}
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}
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// All other arguments (including other floating-point arguments) will be passed in integer
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// registers.
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if (IsCurrentParamALongOrDouble()) {
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if (itr_slots_ == 0u) {
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return MipsManagedRegister::FromRegisterPair(A0_A1);
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} else {
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CHECK_EQ(itr_slots_, 2u);
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return MipsManagedRegister::FromRegisterPair(A2_A3);
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}
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} else {
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return MipsManagedRegister::FromCoreRegister(kJniCoreArgumentRegisters[itr_slots_]);
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}
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}
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FrameOffset MipsJniCallingConvention::CurrentParamStackOffset() {
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CHECK_GE(itr_slots_, kMaxIntLikeRegisterArguments);
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size_t offset = displacement_.Int32Value() - OutArgSize() + (itr_slots_ * kFramePointerSize);
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CHECK_LT(offset, OutArgSize());
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return FrameOffset(offset);
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}
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size_t MipsJniCallingConvention::NumberOfOutgoingStackArgs() {
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size_t static_args = HasSelfClass() ? 1 : 0; // Count jclass.
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// Regular argument parameters and this.
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size_t param_args = NumArgs() + NumLongOrDoubleArgs(); // Twice count 8-byte args.
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// Count JNIEnv* less arguments in registers.
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size_t internal_args = (HasJniEnv() ? 1 : 0);
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size_t total_args = static_args + param_args + internal_args;
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return total_args - std::min(kMaxIntLikeRegisterArguments, static_cast<size_t>(total_args));
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}
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} // namespace mips
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} // namespace art
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