/*
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* drivers/input/sensor/sunxi_gpadc.h
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*
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* Copyright (C) 2016 Allwinner.
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* fuzhaoke <fuzhaoke@allwinnertech.com>
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*
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* SUNXI GPADC Controller Driver Header
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef SUNXI_GPADC_H
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#define SUNXI_GPADC_H
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#define GPADC_DEV_NAME ("sunxi-gpadc")
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#define OSC_24MHZ (24000000UL)
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#define MAX_SR (100000UL)
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#define MIN_SR (400UL)
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#define DEFAULT_SR (1000UL)
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#define VOL_RANGE (1800000UL) /* voltage range 0~2.3v, unit is uv */
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/* GPADC register offset */
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#define GP_SR_REG (0x00) /* GPADC Sample Rate config register */
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#define GP_CTRL_REG (0x04) /* GPADC control register */
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#define GP_CS_EN_REG (0x08) /* GPADC compare and select enable register */
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#define GP_FIFO_INTC_REG (0x0c) /* GPADC FIFO interrupt config register */
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#define GP_FIFO_INTS_REG (0x10) /* GPADC FIFO interrupt status register */
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#define GP_FIFO_DATA_REG (0X14) /* GPADC FIFO data register */
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#define GP_CB_DATA_REG (0X18) /* GPADC calibration data register */
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#define GP_DATAL_INTC_REG (0x20)
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#define GP_DATAH_INTC_REG (0x24)
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#define GP_DATA_INTC_REG (0x28)
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#define GP_DATAL_INTS_REG (0x30)
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#define GP_DATAH_INTS_REG (0x34)
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#define GP_DATA_INTS_REG (0x38)
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#define GP_CH0_CMP_DATA_REG (0x40) /* GPADC channal 0 compare data register */
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#define GP_CH1_CMP_DATA_REG (0x44) /* GPADC channal 1 compare data register */
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#define GP_CH2_CMP_DATA_REG (0x48) /* GPADC channal 2 compare data register */
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#define GP_CH3_CMP_DATA_REG (0x4c) /* GPADC channal 3 compare data register */
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#define GP_CH0_DATA_REG (0x80) /* GPADC channal 0 data register */
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#define GP_CH1_DATA_REG (0x84) /* GPADC channal 1 data register */
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#define GP_CH2_DATA_REG (0x88) /* GPADC channal 2 data register */
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#define GP_CH3_DATA_REG (0x8c) /* GPADC channal 3 data register */
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/* GP_SR_REG default value: 0x01df_002f 50KHZ */
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#define GP_SR_CON (0xffff << 16) /* sample_rate = clk_in/(n+1) = 24MHZ/(0x1df + 1) = 50KHZ */
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/* GP_CTRL_REG default value:0x0000_0000 */
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#define GP_FIRST_CONCERT_DLY (0xff<<24) /* the delay time of the first time */
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#define GP_CALI_EN (1 << 17) /* enable calibration */
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#define GP_ADC_EN (1 << 16) /* GPADC function enable, 0: disable, 1: enable */
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#define GP_MODE_SELECT (3 << 8) /*00:single conversion mode, 01:single-cycle conversion mode, 10:continuous mode, 11:burst mode*/
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#define GP_CH3_CMP_EN (1 << 19) /* channale 3 compare enable, 0:disable, 1:enable */
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#define GP_CH2_CMP_EN (1 << 18) /* channale 2 compare enable, 0:disable, 1:enable */
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#define GP_CH1_CMP_EN (1 << 17) /* channale 1 compare enable, 0:disable, 1:enable */
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#define GP_CH0_CMP_EN (1 << 16) /* channale 0 compare enable, 0:disable, 1:enable */
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#define GP_CH3_SELECT (1 << 3) /* channale 3 select enable, 0:disable, 1:enable */
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#define GP_CH2_SELECT (1 << 2) /* channale 2 select enable, 0:disable, 1:enable */
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#define GP_CH1_SELECT (1 << 1) /* channale 1 select enable, 0:disable, 1:enable */
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#define GP_CH0_SELECT (1 << 0) /* channale 0 select enable, 0:disable, 1:enable */
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/* GP_FIFO_INTC_REG default value: 0x0000_0f00 */
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#define FIFO_OVER_IRQ_EN (1 << 17) /* fifo over run irq enable, 0:disable, 1:enable */
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#define FIFO_DATA_IRQ_EN (1 << 16) /* fifo data irq enable, 0:disable, 1:enable */
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#define FIFO_FLUSH (1 << 4) /* write 1 to flush TX FIFO, self clear to 0 */
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/* GP_FIFO_INTS_REG default value: 0x0000_0000 */
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#define FIFO_OVER_PEND (1 << 17) /* fifo over pending flag, 0:no pending irq, 1: over pending, need write 1 to clear flag */
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#define FIFO_DATA_PEND (1 << 16) /* fifo data pending flag, 0:no pending irq, 1:data pending, need write 1 to clear flag */
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#define FIFO_CNT (0x3f << 8) /* the data count in fifo */
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/* GP_FIFO_DATA_REG default value: 0x0000_0000 */
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#define GP_FIFO_DATA (0xfff << 0) /* GPADC data in fifo */
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/* GP_CB_DATA_REG default value: 0x0000_0000 */
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#define GP_CB_DATA (0xfff << 0) /* GPADC calibration data */
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/* GP_INTC_REG default value: 0x0000_0000 */
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#define GP_CH3_LOW_IRQ_EN (1 << 11) /* 0:disable, 1:enable */
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#define GP_CH2_LOW_IRQ_EN (1 << 10)
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#define GP_CH1_LOW_IRQ_EN (1 << 9)
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#define GP_CH0_LOW_IRQ_EN (1 << 8)
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#define GP_CH3_HIG_IRQ_EN (1 << 7)
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#define GP_CH2_HIG_IRQ_EN (1 << 6)
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#define GP_CH1_HIG_IRQ_EN (1 << 5)
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#define GP_CH0_HIG_IRQ_EN (1 << 4)
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#define GP_CH3_DATA_IRQ_EN (1 << 3)
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#define GP_CH2_DATA_IRQ_EN (1 << 2)
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#define GP_CH1_DATA_IRQ_EN (1 << 1)
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#define GP_CH0_DATA_IRQ_EN (1 << 0)
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/* GP_INTS_REG default value: 0x0000_0000 */
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#define GP_CH3_LOW (1 << 3) /* 0:no pending, 1:pending */
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#define GP_CH2_LOW (1 << 2)
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#define GP_CH1_LOW (1 << 1)
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#define GP_CH0_LOW (1 << 0)
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#define GP_CH3_HIG (1 << 3)
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#define GP_CH2_HIG (1 << 2)
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#define GP_CH1_HIG (1 << 1)
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#define GP_CH0_HIG (1 << 0)
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#define GP_CH3_DATA (1 << 3)
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#define GP_CH2_DATA (1 << 2)
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#define GP_CH1_DATA (1 << 1)
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#define GP_CH0_DATA (1 << 0)
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/* GP_CH0_CMP_DATA_REG default value 0x0bff_0400 */
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#define GP_CH0_CMP_HIG_DATA (0xfff << 16) /* channel 0 hight voltage data */
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#define GP_CH0_CMP_LOW_DATA (0xfff << 0) /* channel 0 low voltage data */
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/* GP_CH1_CMP_DATA_REG default value 0x0bff_0400 */
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#define GP_CH1_CMP_HIG_DATA (0xfff << 16) /* channel 1 hight voltage data */
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#define GP_CH1_CMP_LOW_DATA (0xfff << 0) /* channel 1 low voltage data */
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/* GP_CH2_CMP_DATA_REG default value 0x0bff_0400 */
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#define GP_CH2_CMP_HIG_DATA (0xfff << 16) /* channel 2 hight voltage data */
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#define GP_CH2_CMP_LOW_DATA (0xfff << 0) /* channel 2 low voltage data */
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/* GP_CH3_CMP_DATA_REG default value 0x0bff_0400 */
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#define GP_CH3_CMP_HIG_DATA (0xfff << 16) /* channel 3 hight voltage data */
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#define GP_CH3_CMP_LOW_DATA (0xfff << 0) /* channel 3 low voltage data */
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/* GP_CH0_DATA_REG default value:0x0000_0000 */
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#define GP_CH0_DATA_MASK (0xfff << 0) /* channel 0 data mask */
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/* GP_CH1_DATA_REG default value:0x0000_0000 */
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#define GP_CH1_DATA_MASK (0xfff << 0) /* channel 1 data mask */
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/* GP_CH2_DATA_REG default value:0x0000_0000 */
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#define GP_CH2_DATA_MASK (0xfff << 0) /* channel 2 data mask */
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/* GP_CH3_DATA_REG default value:0x0000_0000 */
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#define GP_CH3_DATA_MASK (0xfff << 0) /* channel 3 data mask */
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#define GP_CALIBRATION_ENABLE (0x1 << 17)
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#define CHANNEL_0_SELECT 0x01
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#define CHANNEL_1_SELECT 0x02
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#define CHANNEL_2_SELECT 0x04
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#define CHANNEL_3_SELECT 0x08
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#define CHANNEL_MAX_NUM 8
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#define KEY_MAX_CNT (13)
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#define VOL_NUM KEY_MAX_CNT
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#define MAXIMUM_INPUT_VOLTAGE 1800
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#define DEVIATION 100
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#define SUNXIKEY_DOWN (MAXIMUM_INPUT_VOLTAGE-DEVIATION)
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#define SUNXIKEY_UP SUNXIKEY_DOWN
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#define MAXIMUM_SCALE 128
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#define SCALE_UNIT (MAXIMUM_INPUT_VOLTAGE/MAXIMUM_SCALE)
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#define SAMPLING_FREQUENCY 10
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enum {
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DEBUG_INFO = 1U << 0,
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DEBUG_RUN = 1U << 1,
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};
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enum gp_select_mode {
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GP_SINGLE_MODE = 0,
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GP_SINGLE_CYCLE_MODE,
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GP_CONTINUOUS_MODE,
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GP_BURST_MODE,
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};
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enum gp_channel_id {
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GP_CH_0 = 0,
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GP_CH_1,
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GP_CH_2,
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GP_CH_3,
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};
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struct sunxi_config {
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u32 channel_select;
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u32 channel_data_select;
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u32 channel_compare_select;
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u32 channel_cld_select;
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u32 channel_chd_select;
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u32 channel_compare_lowdata[CHANNEL_MAX_NUM];
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u32 channel_compare_higdata[CHANNEL_MAX_NUM];
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};
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struct sunxi_gpadc {
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struct platform_device *pdev;
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struct input_dev *input_gpadc[CHANNEL_MAX_NUM];
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struct sunxi_config gpadc_config;
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struct clk *mclk;
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struct clk *pclk;
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void __iomem *reg_base;
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int irq_num;
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u32 channel_num;
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u32 scankeycodes[KEY_MAX_CNT];
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u32 gpadc_sample_rate;
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char key_name[16];
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u32 key_num;
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u8 key_cnt;
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u8 compare_before;
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u8 compare_later;
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u8 key_code;
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u32 key_val;
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};
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struct status_reg {
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char *pst;
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char *ped;
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unsigned char channel;
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unsigned char val;
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};
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struct vol_reg {
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char *pst;
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char *ped;
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unsigned char index;
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unsigned long vol;
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};
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struct sr_reg {
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char *pst;
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unsigned long val;
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};
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struct filter_reg {
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char *pst;
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unsigned long val;
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};
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#endif
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