/*
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* Contains CPU specific branch predictor invalidation sequences
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*
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* Copyright (C) 2018 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/arm-smccc.h>
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.macro ventry target
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.rept 31
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nop
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.endr
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b \target
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.endm
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.macro vectors target
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ventry \target + 0x000
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ventry \target + 0x080
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ventry \target + 0x100
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ventry \target + 0x180
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ventry \target + 0x200
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ventry \target + 0x280
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ventry \target + 0x300
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ventry \target + 0x380
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ventry \target + 0x400
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ventry \target + 0x480
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ventry \target + 0x500
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ventry \target + 0x580
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ventry \target + 0x600
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ventry \target + 0x680
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ventry \target + 0x700
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ventry \target + 0x780
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.endm
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.align 11
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ENTRY(__bp_harden_hyp_vecs_start)
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.rept 4
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vectors __kvm_hyp_vector
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.endr
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ENTRY(__bp_harden_hyp_vecs_end)
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.macro smccc_workaround_1 inst
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sub sp, sp, #(8 * 4)
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stp x2, x3, [sp, #(8 * 0)]
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stp x0, x1, [sp, #(8 * 2)]
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mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1
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\inst #0
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ldp x2, x3, [sp, #(8 * 0)]
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ldp x0, x1, [sp, #(8 * 2)]
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add sp, sp, #(8 * 4)
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.endm
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ENTRY(__smccc_workaround_1_smc_start)
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smccc_workaround_1 smc
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ENTRY(__smccc_workaround_1_smc_end)
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ENTRY(__smccc_workaround_1_hvc_start)
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smccc_workaround_1 hvc
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ENTRY(__smccc_workaround_1_hvc_end)
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