Þ Ó ü H I L K K 4 ä ½ 3 × u / ´ 7 ä k } B I [ Ú 6 [ Ä ¯ ( D ( m ( 1 ¿ % ñ % 3 = ( q 2 ? Í " / / ? . o ª ¸ Ó í 6 I ] ( { ¤ º Ú ó . * @
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k % v ) % Æ ! ì ! $ 0 U : q 9 ¬ æ " # 6 I _ u ¡ ¹ Ò ð % # ( + L + x 1 ¤ 1 Ö + 1 4 1 f % ´ Ú î ! < U + j ! ° " Ò + õ ! B c ¤ ! ¸ Ú ê ; Y w ³ Ä Û " ë ! .! K! f! % y! ! µ! Í! â! ù! " !" -" ! 9" [" $ l" % " 2 ·" 2 ê" 2 # P# g# w# # # ¡# ' Å# í# $ - %$ ; S$ / $ ¿$ É$ æ$ î$ þ$ % &% G% `% x% É % Z' > \' = ' / Ù' ( 5 ¢( z Ø( S) ì) (
* 2 ®* z á* T \+ 1 ±+ l ã+ D P, i , k ÿ, k k- s ×- ( K. ( t. ( . * Æ. ( ñ. ( / / C/ + s/ + / 9 Ë/ 0 0 -0 0 <0 / m0 0 ¬0 »0 Õ0 ê0 1 1 1 /1 A1 S1 , n1 1 ³1 Ê1 * æ1 * 2 <2 " R2 u2 2 " 2 Ã2 â2 ý2 3 63 E O3 E 3 Û3 ó3 4 !4 34 H4 ]4 r4 4 £4 % ³4 Ù4 ' ê4 ' 5 1 :5 1 l5 9 5 9 Ø5 1 6 9 D6 9 ~6 ¸6 0 Ñ6 7 7 .7 I7 g7 7 ' 7 Á7 Î7 á7 # ñ7 8 ,8 C8 Z8 p8 8 8 ²8 Å8 Ò8 è8 ü8 9 $9 89 H9 X9 b9 ~9 9 9 ´9 $ Ê9 ï9 : : 7: P: f: |:
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: ! : ·: Ç: $ Ý: . ; / 1; . a; ; ¦; ³; Ï; ß; û; < 4< 3 S< 7 < 4 ¿< ô< þ< = = *= 9= Q= m= = = ; G \ u 8 C g 6 t % 4 r . 9 S ` I E - y x 3 Y
X j 7 & < = + / v , O M T s { W ? : h ! D Q p m A V U @ Z H B # e F k 5 ) ( z l } 2 " P K f | 0 L 1 * i ~ w o N a b >
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' $ c q _ J ^ [ n R d ]
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For the options above, The following values are supported for "ARCH":
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For the options above, the following values are supported for "ABI":
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aliases Do print instruction aliases.
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cp0-names=ARCH Print CP0 register names according to
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specified architecture.
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Default: based on binary being disassembled.
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debug_dump Temp switch for debug trace.
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fpr-names=ABI Print FPR names according to specified ABI.
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Default: numeric.
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gpr-names=ABI Print GPR names according to specified ABI.
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Default: based on binary being disassembled.
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hwr-names=ARCH Print HWR names according to specified
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architecture.
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Default: based on binary being disassembled.
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msa Recognize MSA instructions.
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no-aliases Don't print instruction aliases.
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reg-names=ABI Print GPR and FPR names according to
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specified ABI.
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reg-names=ARCH Print CP0 register and HWR names according to
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specified architecture.
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virt Recognize the virtualization ASE instructions.
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The following AARCH64 specific disassembler options are supported for use
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with the -M switch (multiple options should be separated by commas):
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The following ARM specific disassembler options are supported for use with
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the -M switch:
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The following MIPS specific disassembler options are supported for use
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with the -M switch (multiple options should be separated by commas):
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The following PPC specific disassembler options are supported for use with
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the -M switch:
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The following S/390 specific disassembler options are supported for use
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with the -M switch (multiple options should be separated by commas):
|
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The following i386/x86-64 specific disassembler options are supported for use
|
with the -M switch (multiple options should be separated by commas):
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addr16 Assume 16bit address size
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addr32 Assume 32bit address size
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addr64 Assume 64bit address size
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att Display instruction in AT&T syntax
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data16 Assume 16bit data size
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data32 Assume 32bit data size
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esa Disassemble in ESA architecture mode
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i8086 Disassemble in 16bit mode
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intel Display instruction in Intel syntax
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suffix Always display instruction suffix in AT&T syntax
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# <dis error: %08lx> $<undefined> %02x *unknown* %dsp16() takes a symbolic address, not a number %dsp8() takes a symbolic address, not a number %s: Error: %s: Warning: 'ROR' operator not allowed (DP) offset out of range. (SP) offset out of range. (unknown) *unknown* 21-bit offset out of range <function code %d> <illegal precision> <internal disassembler error> <internal error in opcode table: %s %s>
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<unknown register %d> Address 0x%s is out of bounds.
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Bad immediate expression Bad register in postincrement Bad register in preincrement Bad register name Don't know how to specify # dependency %s
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Hmmmm 0x%x Immediate is out of range -128 to 127 Immediate is out of range -32768 to 32767 Immediate is out of range -512 to 511 Immediate is out of range -7 to 8 Immediate is out of range -8 to 7 Immediate is out of range 0 to 65535 Internal disassembler error Internal error: bad sparc-opcode.h: "%s", %#.8lx, %#.8lx
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Internal error: bad sparc-opcode.h: "%s", %#.8lx, %#.8lx
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Label conflicts with `Rx' Label conflicts with register name Missing '#' prefix Missing '.' prefix Missing 'pag:' prefix Missing 'pof:' prefix Missing 'seg:' prefix Missing 'sof:' prefix Operand is not a symbol SR/SelID is out of range Syntax error: No trailing ')' Unknown error %d
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Unrecognised disassembler option: %s
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Unrecognised register name set: %s
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Unrecognized field %d while building insn.
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Unrecognized field %d while decoding insn.
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Unrecognized field %d while getting int operand.
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Unrecognized field %d while getting vma operand.
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Unrecognized field %d while printing insn.
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Unrecognized field %d while setting int operand.
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Unrecognized field %d while setting vma operand.
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Value is not aligned enough W keyword invalid in FR operand slot. W register expected address writeback expected bad instruction `%.50s' bad instruction `%.50s...' branch operand unaligned branch to odd offset branch value not in range and to odd offset branch value out of range displacement value is not aligned displacement value is out of range don't know how to specify %% dependency %s
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dsp:16 immediate is out of range dsp:20 immediate is out of range dsp:24 immediate is out of range dsp:8 immediate is out of range extraneous register floating-point immediate expected illegal bitmask illegal use of parentheses imm10 is out of range imm:6 immediate is out of range immediate is out of range 0-7 immediate is out of range 1-2 immediate is out of range 1-8 immediate is out of range 2-9 immediate offset immediate out of range immediate value immediate value cannot be register immediate value is out of range immediate value out of range invalid conditional option invalid mask field invalid register for stack adjustment invalid register name invalid register offset invalid shift amount invalid shift operator jump hint unaligned junk at end of line missing `)' missing `]' missing mnemonic in syntax string missing register negative immediate value not allowed negative or unaligned offset expected operand out of range (%ld not between %ld and %ld) operand out of range (%ld not between %ld and %lu) operand out of range (%lu not between %lu and %lu) register element index register number register number must be even shift amount shift amount expected to be 0 or 12 shift amount should be a multiple of 16 shift operator expected stack pointer register expected syntax error (expected char `%c', found `%c') syntax error (expected char `%c', found end of instruction) unable to change directory to "%s", errno = %s
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undefined unexpected address writeback unknown unknown 0x%02lx unknown 0x%04lx unknown constraint `%c' unrecognized form of instruction unrecognized instruction vector5 is out of range vector8 is out of range Project-Id-Version: opcodes 2.24.90
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Report-Msgid-Bugs-To: bug-binutils@gnu.org
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POT-Creation-Date: 2014-02-10 09:42+1030
|
PO-Revision-Date: 2015-10-30 09:13-0400
|
Last-Translator: Mingye Wang (Arthur2e5) <arthur200126@gmail.com>
|
Language-Team: Chinese (simplified) <i18n-zh@googlegroups.com>
|
Language: zh_CN
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
|
Content-Transfer-Encoding: 8bit
|
Plural-Forms: nplurals=1; plural=0;
|
X-Generator: Poedit 1.8.4
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|
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对äºä»¥ä¸çé项ï¼ä»¥ä¸å¼å¯è¢«ç¨äº "ARCH"ï¼
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对äºä»¥ä¸çé项ï¼ä»¥ä¸å¼å¯è¢«ç¨äº "ABI"ï¼
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aliases è¦æå°æ令å«åã
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fpr-names=ABI æ ¹æ®æå®ç ABI æå°æµ®ç¹å¯åå¨åã
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reg-names=ABI æ ¹æ®æå®ç ABI æå°éç¨å¯åå¨åæµ®ç¹å¯å
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reg-names=ARCH æ ¹æ®æå®çæ¶ææå° CP0 å HWR å¯åå¨åã
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virt è¯å«èæå ASE æ令ã
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ä¸å AARCH64 ç¹å®çåæ±ç¼å¨é项å¯éè¿ -M å¼å
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ä¸å ARM ç¹å®çåæ±ç¼å¨é项å¯éè¿ -M å¼å
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ä¸å PPC ç¹å®çåæ±ç¼å¨é项å¨ä½¿ç¨ -M å¼å
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ä¸å i386/x86-64 ç¹å®çåæ±ç¼å¨é项å¨ä½¿ç¨ -M å¼å
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addr16 åå® 16 ä½å°å大å°
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addr32 åå® 32 ä½å°å大å°
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addr64 åå® 64 ä½å°å大å°
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att ç¨ AT&T è¯æ³æ¾ç¤ºæ令
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data16 åå® 16 ä½æ°æ®å¤§å°
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data32 åå® 32 ä½æ°æ®å¤§å°
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esa å¨ ESA æ¶æ模å¼ä¸åæ±ç¼
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i8086 å¨ 16 ä½æ¨¡å¼ä¸åæ±ç¼
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intel ç¨ Intel è¯æ³æ¾ç¤ºæ令
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suffix å¨ AT&T è¯æ³ä¸å§ç»æ¾ç¤ºæ令åç¼
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# <åæ±ç¼åºé: %08lx> $<æªå®ä¹> %02x *æªç¥* %dsp16() 使ç¨ä¸ä¸ªç¬¦å·å°åï¼èéæ°å %dsp8() 使ç¨ä¸ä¸ªç¬¦å·å°åï¼èéæ°å %sï¼éè¯¯ï¼ %sï¼è¦åï¼ ä¸å
许 'ROR' æä½ç¬¦ (DP) å移éè¶ç (SP) å移éè¶çã (æªç¥) *æªç¥* 21ä½é¿çå移éè¶ç <å½æ°ä»£ç %d> <éæ³ç精度> <åæ±ç¼å¨å
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é¨é误ï¼%s %s>
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<æªç¥çå¯åå¨ %d> å°å 0x%s è¶çã
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å¦... 0x%x ç«å³æ°è¶ç (-128 å° 127) ç«å³æ°è¶ç (-32768 å° 32767) ç«å³æ°è¶ç (-512 å° 511) ç«å³æ°è¶ç (-7 å° 8) ç«å³æ°è¶ç (-8 å° 7) ç«å³æ°è¶ç (0 å° 65535) åæ±ç¼å¨å
é¨é误 å
é¨é误ï¼é误ç sparc-opcode.hï¼â%sâï¼%#.8lxï¼%#.8lx
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å
é¨é误ï¼é误ç sparc-opcode.hï¼â%sâï¼%#.8lxï¼%#.8lx
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æ å·ä¸âRxâå²çª æ å·ä¸å¯åå¨åå²çª 缺失 '#' åç¼ ç¼ºå¤± '.' åç¼ ç¼ºå¤± 'pag:' åç¼ ç¼ºå¤± 'pof:' åç¼ ç¼ºå¤± 'seg:' åç¼ ç¼ºå¤± 'sof:' åç¼ æä½æ°ä¸æ¯ä¸ä¸ªç¬¦å· SR/SelID è¶ç è¯æ³é误ï¼æ²¡æç»å°¾çâ)â æªç¥é误 %d
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æ æ³è¯å«çåæ±ç¼å¨é项ï¼%s
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æ æ³è¯å«çå¯åå¨å称éï¼%s
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å»ºç« insn æ¶éå°æ æ³è¯å«çå段 %dã
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解ç insn æ¶éå°æ æ³è¯å«çå段 %dã
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è·å¾ int æä½æ°æ¶éå°æ æ³è¯å«çå段 %dã
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è·å¾ vma æä½æ°æ¶éå°æ æ³è¯å«çå段 %dã
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æå° insn æ¶éå°æ æ³è¯å«çå段 %dã
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设置 int æä½æ°æ¶éå°æ æ³è¯å«çå段 %dã
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设置 vma æä½æ°æ¶éå°æ æ³è¯å«çå段 %dã
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æ°å¼å¯¹é½ç¨åº¦ä¸å¤ W å
³é®åéæ³ï¼å¨ FR æä½æ°æ§½ä½ä¸ã é¢æç W å¯åå¨ é¢æçå°ååå é误çæ令â%.50sâ é误çæ令â%.50s...â åæ¯æä½æ°æªå¯¹é½ 跳转å移é为å¥æ° 跳转è¶çä¸è·³è½¬å移é为å¥æ° 跳转è¶ç å移å¼æªå¯¹é½ å移å¼è¶ç ä¸ç¥éå¦ä½æå® %% ä¾èµ %s
|
dsp:16 ç«å³æ°è¶ç dsp:20 ç«å³æ°è¶ç dsp:24 ç«å³æ°è¶ç dsp:8 ç«å³æ°è¶ç å¤ä½å¯åå¨ é¢æçæµ®ç¹å¸¸éç«å³æ° éæ³çä½æ©ç æ¬å·ç¨æ³éæ³ imm10 è¶ç imm:6 ç«å³æ°è¶ç ç«å³æ°è¶ç 0-7 ç«å³æ°è¶ç 1-2 ç«å³æ°è¶ç 1-8 ç«å³æ°è¶ç 2-9 ç«å³æ°å移 ç«å³æ°è¶ç ç«å³æ° ç«å³æ°ä¸è½æ¯å¯åå¨ ç«å³æ°è¶ç ç«å³æ°è¶ç æ æçæ¡ä»¶é项 æ æçæ©ç å段 ç¨äºè°æ´å æ çå¯åå¨æ æ æ æå¯åå¨å æ æçå¯åå¨å移é æ æç移ä½æä½æ° æ æç移ä½æä½ç¬¦ 跳转æ示æªå¯¹é½ è¡å°¾æåå¾å符 缺å°â)â ç¼ºå° `]' è¯æ³å符串ä¸æ²¡æå©è®°ç¬¦ 缺失å¯åå¨ ä¸å
许è´ç«å³æ° é¢æçè´ææªå¯¹é½çå移é æä½æ°è¶ç(%ld ä¸å¨ %ld å %ld ä¹é´) æä½æ°è¶ç (%ld ä¸å¨ %ld å %lu ä¹é´) æä½æ°è¶ç(%lu ä¸å¨ %lu å %lu ä¹é´) å¯åå¨å
ç´ ä¸æ å¯åå¨æ° å¯åå¨æ°å¿
é¡»æ¯å¶æ° 移ä½æä½æ° 移ä½éé¢è®¡ä¸º 0 æ 12 移ä½éåºè¯¥æ¯ 16 çåæ° é¢æç移ä½æä½ç¬¦ é¢æçå æ æéå¯åå¨ è¯æ³é误(éè¦å符â%câï¼å¾å°â%câ) è¯æ³é误(éè¦å符â%câï¼å´å°è¾¾æ令尾) æ æ³å°å½åç®å½åæ¢è³â%sâï¼errno = %s
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æªå®ä¹ æå¤çå°ååå æªç¥ æªç¥ 0x%02lx æªç¥ 0x%04lx æªç¥ç约æâ%câ æ æ³è¯å«çæä»¤æ ¼å¼ æ æ³è¯å«çæ令 vector5 è¶ç vector8 è¶ç
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