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| #ifndef _ASM_ARM_PERF_REGS_H
| #define _ASM_ARM_PERF_REGS_H
|
| enum perf_event_arm_regs {
| PERF_REG_ARM_R0,
| PERF_REG_ARM_R1,
| PERF_REG_ARM_R2,
| PERF_REG_ARM_R3,
| PERF_REG_ARM_R4,
| PERF_REG_ARM_R5,
| PERF_REG_ARM_R6,
| PERF_REG_ARM_R7,
| PERF_REG_ARM_R8,
| PERF_REG_ARM_R9,
| PERF_REG_ARM_R10,
| PERF_REG_ARM_FP,
| PERF_REG_ARM_IP,
| PERF_REG_ARM_SP,
| PERF_REG_ARM_LR,
| PERF_REG_ARM_PC,
| PERF_REG_ARM_MAX,
| };
| #endif /* _ASM_ARM_PERF_REGS_H */
|
|
