//===--------------------- DispatchStage.cpp --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file models the dispatch component of an instruction pipeline.
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///
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/// The DispatchStage is responsible for updating instruction dependencies
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/// and communicating to the simulated instruction scheduler that an instruction
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/// is ready to be scheduled for execution.
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///
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//===----------------------------------------------------------------------===//
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#include "DispatchStage.h"
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#include "HWEventListener.h"
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#include "Scheduler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
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ArrayRef<unsigned> UsedRegs) {
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LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
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notifyEvent<HWInstructionEvent>(HWInstructionDispatchedEvent(IR, UsedRegs));
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}
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bool DispatchStage::checkPRF(const InstRef &IR) {
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SmallVector<unsigned, 4> RegDefs;
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for (const std::unique_ptr<WriteState> &RegDef :
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IR.getInstruction()->getDefs())
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RegDefs.emplace_back(RegDef->getRegisterID());
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const unsigned RegisterMask = PRF.isAvailable(RegDefs);
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// A mask with all zeroes means: register files are available.
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if (RegisterMask) {
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notifyEvent<HWStallEvent>(
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HWStallEvent(HWStallEvent::RegisterFileStall, IR));
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return false;
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}
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return true;
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}
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bool DispatchStage::checkRCU(const InstRef &IR) {
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const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps;
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if (RCU.isAvailable(NumMicroOps))
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return true;
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notifyEvent<HWStallEvent>(
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HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
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return false;
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}
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bool DispatchStage::checkScheduler(const InstRef &IR) {
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HWStallEvent::GenericEventType Event;
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const bool Ready = SC.canBeDispatched(IR, Event);
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if (!Ready)
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notifyEvent<HWStallEvent>(HWStallEvent(Event, IR));
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return Ready;
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}
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void DispatchStage::updateRAWDependencies(ReadState &RS,
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const MCSubtargetInfo &STI) {
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SmallVector<WriteRef, 4> DependentWrites;
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collectWrites(DependentWrites, RS.getRegisterID());
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RS.setDependentWrites(DependentWrites.size());
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// We know that this read depends on all the writes in DependentWrites.
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// For each write, check if we have ReadAdvance information, and use it
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// to figure out in how many cycles this read becomes available.
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const ReadDescriptor &RD = RS.getDescriptor();
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const MCSchedModel &SM = STI.getSchedModel();
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const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
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for (WriteRef &WR : DependentWrites) {
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WriteState &WS = *WR.getWriteState();
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unsigned WriteResID = WS.getWriteResourceID();
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int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
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WS.addUser(&RS, ReadAdvance);
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}
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}
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void DispatchStage::dispatch(InstRef IR) {
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assert(!CarryOver && "Cannot dispatch another instruction!");
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Instruction &IS = *IR.getInstruction();
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const InstrDesc &Desc = IS.getDesc();
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const unsigned NumMicroOps = Desc.NumMicroOps;
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if (NumMicroOps > DispatchWidth) {
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assert(AvailableEntries == DispatchWidth);
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AvailableEntries = 0;
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CarryOver = NumMicroOps - DispatchWidth;
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} else {
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assert(AvailableEntries >= NumMicroOps);
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AvailableEntries -= NumMicroOps;
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}
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// A dependency-breaking instruction doesn't have to wait on the register
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// input operands, and it is often optimized at register renaming stage.
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// Update RAW dependencies if this instruction is not a dependency-breaking
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// instruction. A dependency-breaking instruction is a zero-latency
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// instruction that doesn't consume hardware resources.
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// An example of dependency-breaking instruction on X86 is a zero-idiom XOR.
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bool IsDependencyBreaking = IS.isDependencyBreaking();
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for (std::unique_ptr<ReadState> &RS : IS.getUses())
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if (RS->isImplicitRead() || !IsDependencyBreaking)
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updateRAWDependencies(*RS, STI);
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// By default, a dependency-breaking zero-latency instruction is expected to
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// be optimized at register renaming stage. That means, no physical register
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// is allocated to the instruction.
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bool ShouldAllocateRegisters =
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!(Desc.isZeroLatency() && IsDependencyBreaking);
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SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles());
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for (std::unique_ptr<WriteState> &WS : IS.getDefs()) {
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PRF.addRegisterWrite(WriteRef(IR.first, WS.get()), RegisterFiles,
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ShouldAllocateRegisters);
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}
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// Reserve slots in the RCU, and notify the instruction that it has been
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// dispatched to the schedulers for execution.
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IS.dispatch(RCU.reserveSlot(IR, NumMicroOps));
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// Notify listeners of the "instruction dispatched" event.
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notifyInstructionDispatched(IR, RegisterFiles);
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}
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void DispatchStage::cycleStart() {
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AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
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CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
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}
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bool DispatchStage::execute(InstRef &IR) {
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const InstrDesc &Desc = IR.getInstruction()->getDesc();
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if (!isAvailable(Desc.NumMicroOps) || !canDispatch(IR))
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return false;
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dispatch(IR);
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return true;
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}
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#ifndef NDEBUG
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void DispatchStage::dump() const {
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PRF.dump();
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RCU.dump();
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}
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#endif
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} // namespace mca
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